Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-30
2008-08-12
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07412668
ABSTRACT:
A method for noise suppression for a system implementation of an integrated circuit design is described. First clock operating parameters for logic blocks of the integrated circuit design are obtained. Second clock operating parameters for input/output banks of the integrated circuit design are obtained. At least one switching frequency associated with at least one power supply source is obtained. First and second capacitor values for the at least one power supply source are determined responsive to the first clock operating parameters, the second clock operating parameters, and the at least one switching frequency. The first capacitor values are associated with a first frequency range of operation and the second capacitor values are associated with a second frequency range of operation which is higher than the first frequency range of operation. Third capacitor values for suppression of anti-resonances are determined.
REFERENCES:
patent: 5519353 (1996-05-01), Rainal
patent: 5534791 (1996-07-01), Mattos et al.
patent: 6687881 (2004-02-01), Gauthier et al.
patent: 7047515 (2006-05-01), Vitek et al.
patent: 7092292 (2006-08-01), Mokhlesi et al.
patent: 7254797 (2007-08-01), Garlepp
patent: 7278046 (2007-10-01), Chang
patent: 7287205 (2007-10-01), Lin et al.
patent: 7302664 (2007-11-01), Haridass et al.
patent: 7313771 (2007-12-01), Reddy et al.
patent: 2002/0040466 (2002-04-01), Khazei
patent: 2003/0016049 (2003-01-01), Wei
patent: 2004/0062301 (2004-04-01), Yamaguchi et al.
patent: 2005/0144580 (2005-06-01), Berkram et al.
patent: 2005/0283749 (2005-12-01), Yeh
patent: 2006/0158828 (2006-07-01), Amey et al.
patent: 2006/0184904 (2006-08-01), Murgai et al.
patent: 2006/0194366 (2006-08-01), Lee et al.
patent: 2006/0225009 (2006-10-01), Reddy et al.
patent: 2007/0069762 (2007-03-01), Zivanovic
patent: 2007/0070733 (2007-03-01), Chang
patent: 2007/0102811 (2007-05-01), Swaminathan et al.
patent: 2007/0109827 (2007-05-01), DelaCruz
patent: 2007/0291441 (2007-12-01), Inoue et al.
patent: 01222319 (1989-09-01), None
U.S. Appl. No. 10/691,151, filed Oct. 21, 2003, Duong.
Hobbs et al., “Simulataneous Switching Noise Suppression for High Speed Systems Using Embedded Decoupling”, Proceedings of 51st Electronic Components and Technology Conference, May 29-Jun 1, 2001, pp. 339-343.
Tang et al., “Delay Uncertainty Due to On-Chip Simultaneous Switching Noise in High Performance CMOS Integrated Circuits”, 2000 IEEE Workshop on Signal Processing Systems, Oct. 11-13, 2000, pp. 633-642.
Hajj, Simultaneous Switching Noise, and Reliability Analyses of VLSI Core Logic, Electrical Performance of Electronic Packaging, Oct. 25-27, 1999, p. 147.
Osorio et al., “255 CBGA Electrical Performance Comparison Through Package Electrical Characterization and System Simulations”, Electrical Performance of Electronic Packaging, Oct. 2-4, 1995, pp. 95-97.
Jou et al., “Low Switching Noise and Load-Adaptive Output Buffer Design Techniques”, IEEE Journal of Solid-State Circuits, vol. 36, No. 8, Aug. 2001, pp. 1239-1249.
11/343,415, Duong, Anthony T., filed Jan. 30, 2006, “Integrated System Noise Management - System Level”, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
11/344, 423 Duong, Anthony T., filed Jan. 30, 2006, “Integrated System Noise Management - Bounce Voltage”, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
11/344,313, Duong, Anthony T., filed Jan. 30, 2006, “Integrated System Noise Management - Clock Jitter”, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Do Thuan
Webostad W. Eric
Xilinx , Inc.
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