Electrical computers and digital data processing systems: input/ – Interrupt processing – Handling vector
Reexamination Certificate
1999-12-30
2002-07-09
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Handling vector
Reexamination Certificate
active
06418498
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of integrating a system management memory into a memory controller for a system management interrupt handler that is independent of both BIOS and operating system.
BACKGROUND OF THE INVENTION
A large majority of today's personal computer systems implement a system management interrupt (SMI). An SMI signal is asserted to a processor to alert the processor that an SMI event has occurred. The SMI signal is typically asserted to the processor by a system logic device that includes a memory controller. The system logic device may assert the SMI signal for any of a large number of possible reasons. For example, the SMI signal may be asserted if a system resource seeks access to a certain range of memory or to a particular input/output address. These memory and input/output addresses can be programmable via a set of registers that typically reside in the system logic device. The SMI signal may also be asserted if certain system events occur. For example, a computer system may be implemented with a variety of timers for timing a variety of system events. The SMI signal may be asserted if any of these timers expire.
An assertion of the SMI signal indicates to the processor that the processor should begin to fetch instructions from an address stored in one of the processor's registers. This register is sometimes referred to as the system management memory base address register. The memory space located at the address indicated by the system management memory base address register may be referred to as system management memory (SMM). The SMM has stored therein an SMI handler routine. The SMI handler may be implemented to perform any of a wide variety of functions. For example, the SMI handler may perform power management functions, or may try to correct system malfunctions.
The SMM, and therefore the SMI handler, is under control of the computer system's Basic Input/Output System (BIOS). The BIOS is typically designed and implemented by one of several BIOS software companies. The SMI handler is typically installed in the computer system during the system manufacturing process.
Often, there is a need to make changes to the SMI handler after the manufacturing process. One such situation can occur when a chipset manufacturer desires to provide a solution for an erratum or desires to either enable new features or disable old features. These desires can be met by altering the SMI handler. However, a chipset manufacturer's product may be utilized in computer systems built by dozens of different computer system manufacturers. Further, these system manufacturers typically use any of a number of BIOS software companies to design and implement the SMI handler. Therefore, if the chipset manufacturer needs to have the SMI handlers modified, it must negotiate with many different parties to have the changes made. The chipset manufacturer may also try to negotiate with operating system vendors to have the operating systems implement the chipset manufacturer's requests. Neither of these alternatives is desirable, in larger part to the large amount of time and effort required to perform the negotiations and to implement the chipset manufacturer's requests.
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Auve Glenn A.
Intel Corporation
Wells Calvin E.
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