Integrated structure layout and layout of interconnections for a

Details Integrated structure layout and layout of interconnections for a Integrated structure layout and layout of interconnections for a

1998-10-16

2000-07-04

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

712 26, 712201, 326 47, 326101, 327565, G06F 1750, G06F 1500, G06F 1900, H01L 2700

Patent

active

060832746

ABSTRACT:
An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The functional blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplexer logic. The data dependency logic receives address signals for a group of instructions and passes dependency information output to the tag assignment logic. The tag assignment logic provides tag information output to the register file port multiplexer logic. The tag assignment logic is arranged on opposite sides of a center channel, so that the tag information output is laid-out in the center channel and is fed directly to the register file port multiplexer logic in a substantially straight path. The register file port multiplexer logic directs the tag information output to a register file address port of a register file.

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