Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-05-04
2002-10-15
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S532000
Reexamination Certificate
active
06465840
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to techniques for polycrystalline silicon (polysilicon) deposition for the fabrication of a semiconductor integrated device, and, more particularly, to the formation of a layer of polysilicon on a dielectric layer.
BACKGROUND OF THE INVENTION
The scaling down toward ever smaller integrated structures and the consequent reduction of operating voltages, as well as of the thickness of dielectric layers for capacitive coupling, aggravates the criticality of residual imperfections in the dielectric. These imperfections occur during the process of formation of the dielectric layer and/or are induced in the dielectric film during the successive steps of fabrication of the integrated device that includes several different thermal treatments.
In highly critical dielectric layers, like for instance in the case of the tunnel oxide in a FLASH or EEPROM memory structure for the capacitive coupling between a floating gate patterned from a deposited polycrystalline silicon layer, eventually doped in-situ, and a drain region of the underlying monocrystalline silicon semiconductor, it is generally accepted that the dielectric properties may be affected by the characteristics of the layers interfacing or being coupled therewith. An interface layer may typically be polycrystalline silicon which is the conductor material interfaced to the dielectric film. Another critical dielectric layer is the so-called “interpoly” dielectric layer for the capacitive coupling between a floating gate patterned from a first level polycrystalline silicon and a control gate patterned from a second level polycrystalline silicon. This influence manifests itself during thermal treatments taking place after the formation of these stacked layers and depends from the way these layers were formed (temperatures, pressure, gas flow rates, residence times, growth rate).
SUMMARY OF THE INVENTION
With identical fabrication conditions, it has been observed that the reliability of a dielectric layer for instance of a tunnel oxide, in terms of breakdown, is markedly influenced by certain characteristics of the electrically conducting layer deposited over the dielectric. Surprisingly, it has been found that a layer of tunnel oxide (SiO
2
) performs better the larger the grain size or the size of single crystal domains or crystallites of the conducting material deposited over the oxide layer. Such a conducting material is typically a doped polycrystalline silicon (polysilicon) layer.
It has been established further that a highly efficient structure is defined by interfacing, to a dielectric layer for capacitive coupling, an electrically conductive layer of doped polycrystalline silicon or equivalent electrically conductive material, having crystallization grains whose dimensions are substantially of the same size of the area of capacitive coupling to be defined. This means that, on such a coupling area, the conductive layer is of an ideally unigranular polycrystalline material or that there exists an extremely small number of distinct crystalline domains or crystallites.
It has been found that such a crystalline structure, for example of polycrystalline silicon, may be obtained by depositing an essentially amorphous silicon film at a sufficiently low temperature and crystallizing the deposited film by an annealing step conducted at a sufficiently low temperature lower than the deposition temperature, typically below 650° C. The technological research aimed to fulfill such a requirement through economically viable techniques compatible with productivity requirements, has led to establish that is it possible to form layers of polycrystalline silicon, doped or undoped, with grains of dimensions comparable to those of the relevant structural features that are defined in modern fabrication processes of integrated circuits. This may be done by using a chemical vapor phase deposition reactor capable of being operated at relatively high pressures and with controlled rapid temperature variations.
REFERENCES:
patent: 4214918 (1980-07-01), Gat et al.
patent: 4874716 (1989-10-01), Rao
patent: 5031010 (1991-07-01), Mikata et al.
patent: 5563093 (1996-10-01), Koda et al.
patent: 5614257 (1997-03-01), Beinglass et al.
patent: 5949102 (1999-09-01), Saida et al.
patent: 0 274 390 (1988-01-01), None
Patent Abstracts of Japan, vol. 096, No. 010, Oct. 31, 1996, and JP 08 153808A (Oki Electric Ind. Co., Ltd.), Jun. 11, 1996.
Patent Abstracts of Japan, vol. 013, No. 016, Jan. 13, 1989, and JP 63 221681A (Mitsubishi Electric Corp.), Sep. 14, 1988 AM.
Patent Abstracts of Japan, vol. 014, No. 178, Apr. 10, 1990, and JP 02 031468A (NEC Corp. ), Feb. 1, 1990.
Kazuhiro Shimizu, et al., “High-Mobility Poly-Si Thin-Film Transistors Fabricated by a Novel Excimer Laser Crystallization Method,” IEEE Transactions on Electron Devices, vol. 40, No. 1, Jan. 1993, pp. 112-117.
Munetaka Koda, et al., “Improving Gate Oxide Integrity in p+pMOSFET by Using Large Grain Size Polysilicon Gate,” Proceedings of the International Electron Devices Meeting, Washington, Dec. 5-8, 1993, Institute of Electrical and Electronic Engineers, pp. 471-474.
Ferroni Giovanni
Queirolo Giuseppe
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Prenty Mark V.
SGS--Thomson Microelectronics S.r.l.
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