Metal fusion bonding – Process – With pretreating other than heating or cooling of work part...
Reexamination Certificate
2001-06-12
2003-06-03
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
With pretreating other than heating or cooling of work part...
C228S033000, C228S049500, C228S209000, C228S215000, C228S254000, C204S267000, C204S269000
Reexamination Certificate
active
06572010
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for depositing solder bumps on a substrate.
2. Description of the Background Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI) integrated circuits. The multi-level interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to a success of ULSI and to the continued effort to increase circuit density and quality on individual substrates.
Several methods may be used for forming the necessary electrical interconnections on semiconductor substrates. One method is to utilize lead frames that extend out of a plastics package in which an integrated circuit has been encapsulated in order to connect with an external device. With increasing miniaturization, however, another approach known as “flip-chip” technology has widely come into practice. With “flip-chip” technology, electrical interconnects are provided by means of conductive metal bumps, known as solder bumps, constructed on bond pads that are formed on the top or active surface of the semiconductor substrate. The semiconductor substrate can then be “flipped” and mounted directly to a printed wiring board or other device, with the solder bumps forming the electronic interconnects. “Flip-chip” technology thus eliminates the need for semiconductor packaging and leads to many important advantages over other technologies used to form electrical interconnects including greater miniaturization, better interconnect reliability, higher circuit densities, and cost savings.
“Flip-chip” technology using solder bumps is particularly important for forming interconnects on semiconductor substrates on which copper features have been formed. For several reasons, copper is increasingly used instead of aluminum to form features on semiconductor substrates. As compared with aluminum, copper and its alloys have lower resistivities and significantly higher electromigration resistance. These characteristics support the high current densities experienced at high levels of integration and increase device speed. Copper has become especially favored with trends toward increasing miniaturization of interconnect substrate devices. Attempts at directly bonding wire to copper have proven unsuccessful. Therefore, “flip-chip” technology using solder bumps is employed to form electrical connections on semiconductor substrates on which copper features have been formed.
While several methods of forming solder bumps are available, electroplating has become favored over other methods including screening and evaporation techniques. Evaporation techniques typically involve evaporation of copper chrome and deposition of the material on a semiconductor substrate to form solder bumps. However, evaporation techniques are very expensive and inefficient. With evaporation techniques, typically about half of the material used is wasted. Furthermore, trends toward so-called “very low soft error” microprocesses require the use of so-called “low alpha lead”, which is extremely expensive. The electroplating method of forming solder bumps, by contrast, is simple and efficient. Electroplating takes place only on the desired areas of the semiconductor substrate, so that very little material is wasted.
A semiconductor substrate typically undergoes a number of processing steps prior to the solder bump formation processing sequence. Specifically, the surface of a silicon substrate is metallized with a bonding layer of aluminum or copper. Next, a metal under-barrier layer such as copper is deposited on the bonding layer. A photoresist mask layer is then deposited onto the under-barrier layer. Next, the photoresist mask layer is patterned by a lithographic etch process.
After the substrate has been processed in the above manner, the substrate is electroplated with solder. After that, solvent etching of the photoresist mask layer is performed. Next, a cleaning step is performed during which excess under-barrier layer is removed and the substrate is dried. Finally, the substrate is heated in order to reflow the solder, causing the deposited solder to take the desired hemispherical shape of solder bumps.
Each of the steps detailed above following the lithographic etching of the photoresist mask layer generally requires a different system. One system is required to perform electroplating of the substrate with a metal under-layer, another for electroplating of the substrate with solder, another for solvent etching a photoresist mask layer, another for cleaning the substrate, removing the metal under-layer and drying the substrate, and another to reflow the solder. Utilizing a number of different systems and transferring the substrate from one to another in order to form solder bumps is time-consuming and expensive, and reduces throughput of substrates.
Therefore, a need exists in the art for an integrated apparatus and method for performing all of the processing steps necessary to form solder bumps on a substrate.
SUMMARY OF THE INVENTION
The present invention provides an integrated method and apparatus for forming solder bumps on a substrate. The invention provides an integrated apparatus comprising a plurality of electrolytic cells, a lithographic station, a reflow process chamber and an integrated etch/clean/passthrough (ECP) station. The method comprises introducing a substrate having a photoresist pattern defining a location for depositing solder bumps into a transfer position within the apparatus, the substrate is positioned into a deposition position where an electroplating process is performed to deposit a metal underlayer onto the substrate. After the underlayer has been deposited, the substrate is electroplated with solder in a solder electroplating cell, and then transferred to an integrated ECP station to remove the photoresist and clean the substrate. In the last step, the substrate is heated in a solder reflow chamber to form one or more solder bumps on the substrate.
REFERENCES:
patent: 4654116 (1987-03-01), Spacer
patent: 4950623 (1990-08-01), Dishon
patent: 6013572 (2000-01-01), Hur et al.
patent: 6030512 (2000-02-01), Ihara et al.
patent: 6057234 (2000-05-01), Yamazaki
patent: 6071827 (2000-06-01), Lim et al.
patent: 6130158 (2000-10-01), Hibino
patent: 6144103 (2000-11-01), Miller et al.
patent: 6146984 (2000-11-01), Leibovitz et al.
patent: 6165885 (2000-12-01), Gaynes et al.
patent: 6179200 (2001-01-01), Kung et al.
patent: 6258220 (2001-07-01), Dordi et al.
patent: 6268656 (2001-07-01), Leibovitz et al.
patent: 6426281 (2002-07-01), Lin et al.
patent: 6426556 (2002-07-01), Lin
US 2002/0029961 A1 Dordi et al. Mar. 14, 2002.*
US 2002/0033340 A1 Cheung et al. Mar. 21, 2002.
Cheung Robin
Dordi Yezdi N.
Applied Materials Inc.
Dunn Tom
Moser Patterson & Sheridan
Stoner Kiley S.
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