Integrated semiconductor structure with means to prevent unlimit

Details Integrated semiconductor structure with means to prevent unlimit Integrated semiconductor structure with means to prevent unlimit

1975-12-19

1977-05-17

James, Andrew J.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307200A, 357 48, H02H 1100, H01L 2704

Patent

active

040244172

ABSTRACT:
This describes an integrated semiconductor structure having an epitaxial semiconductor layer, divided into regions by isolation zones and containing active and passive semiconductor devices, of a first conductivity type on a substrate of the opposite second conductivity type. A reference potential and first and second supply voltages are applied to the structure. An additional isolated transistor, in accordance with this invention prevents an unlimited current flow, via the chip isolation junction, from one voltage supply to the other when the power-on sequence for both voltages is undefined. The base of this additional transistor is connected to one of the voltages via an integrated resistor while the other voltage is connected to the emitter and the collector is connected to the substrate via the isolation zone. Thus, the isolation junction can never become forward biased. In addition, this arrangement ensures that the substrate potential is independent of the rate of the above-mentioned substrate current, and perfect isolation is guaranteed under all conditions.

REFERENCES:
patent: 3541357 (1970-11-01), Kram
patent: 3725675 (1973-04-01), Olsen
patent: 3860461 (1975-01-01), Robinette, Jr.
Agusta, "DC Bias for Epi Pocket Pulse Applications", IBM Technical Disclosure Bulletin, vol. 13, No. 6, Nov. 1970, p. 1645.

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