Integrated semiconductor memory with redundant memory cells

Details Integrated semiconductor memory with redundant memory cells Integrated semiconductor memory with redundant memory cells

2007-04-10

2007-04-10

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

11189018

ABSTRACT:
An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

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