Integrated semiconductor memory with a selection transistor...

Details Integrated semiconductor memory with a selection transistor... Integrated semiconductor memory with a selection transistor...

2006-01-31

2006-01-31

Owens, Douglas W. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06992345

ABSTRACT:
An integrated semiconductor memory is disclosed having selection transistors which can be formed at a respective ridge. The ridge can be arranged on an insulation layer. In the ridge the first source/drain region can be formed at one lateral end of the ridge and the second source/drain region can be formed at another lateral end of the ridge. The longitudinal sides of the ridge and a top side of the ridge can be covered with a layer stack including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.

REFERENCES:
patent: 5504027 (1996-04-01), Jeong et al.
patent: 6242772 (2001-06-01), Wahlstrom
patent: 6472702 (2002-10-01), Shen
patent: 2003/0178662 (2003-09-01), Voigt et al.
patent: 36 40363 (1987-08-01), None
patent: 0 703 625 (1996-03-01), None
Yang-Kyu Choi et al., Sub-20nm CMOS FinFet Technologies, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, 2001, 4 pages.

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