Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-12-29
2001-11-20
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C714S030000
Reexamination Certificate
active
06320804
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated semiconductor memory which can be subjected to a memory cell test for determining operative and defective memory cells, and which has a memory unit for storing addresses of defective memory cells.
For the repair of defective memory cells, integrated semiconductor memories generally have redundant memory cells, which are usually combined to form redundant row lines or redundant column lines which can replace regular lines with defective memory cells on an address basis. In this case, the integrated memory is tested, for example by an external testing device or a self-testing device, and programming of the redundant elements is subsequently performed on the basis of a so-called redundancy analysis. A redundancy circuit then has programmable elements, for example in the form of programmable fuses, which serve for storing the address of a line to be replaced.
A semiconductor memory device is tested, for example after the production process, and is subsequently repaired. For this purpose, the addresses of those tested memory cells which were detected as defective are stored in a so-called defect address memory, in order to replace these memory cells in a subsequent step with defect-free redundant memory cells on the basis of the addresses stored. The memory device is in this case generally subjected to a number of tests. Only those memory cells that pass all of the tests are considered in this case to be operative or defect-free. If a memory cell does not pass one or more tests, it is considered to be defective and must be replaced by a defect-free redundant memory cell. In the case of semiconductor memories with a memory cell array in matrix form, which have redundant row lines or redundant column lines, instead of a single memory cell usually an entire row line or column line is replaced by corresponding redundant row lines or column lines.
Since memory cells are subjected to a number of tests, if a particular test is not passed, it must be determined whether the defect address has already been stored because of a failure of a previous test. This determination must be performed before the address of the defective memory cell is stored. If this is the case, the defect address should not be stored a second time, in order to save memory space. The defect addresses may be stored in a separate memory cell array on the chip to be tested. This additional memory cell array is then part of, for example, a self-testing device of the memory chip.
The check to be carried out to ascertain whether a memory cell has already been stored once must not influence the speed with which the memory test is carried out. For example, a parallel comparison of all of the defect addresses already stored with the current defect address, and possibly the subsequent storage of the new address, can in this case take place together in one clock cycle. However, this generally leads to the provision of a considerable amount of circuitry for the defect address memory. A serial comparison of the stored defect addresses with the current defect address is possible only if it can be ensured that the time from detecting one defective memory cell to detecting the next defective memory cell reaches a certain length. This time must be made to be of such a duration to insure that the address of a previously detected defective memory cell can be compared with all of the already stored defect addresses and the address of this detected defective memory cell can possibly be stored before another defective memory cell is detected. Since defective memory cells often occur in rapid succession in a memory cell test, in particular along row lines or column lines, the time periods described usually cannot be maintained.
As long as the number of defective memory cells is small in comparison with the memory size, a memory unit can be provided as a buffer memory, in order to decouple a test of the memory cell array and the storage of the defect addresses. This buffer memory must in this case be large enough to ensure that the addresses of memory cells detected as defective can at any time still be written to be buffer memory. The maximum size of the buffer memory to be provided can be estimated on the basis of the size of the memory to be tested and the existing number of redundant row lines and column lines. For example, all the memory cells along a column line and at the same time as many column lines as it takes to establish that there is no redundant column line available any longer for the repair of defective memory cells along a column line must be tested. This results in a relatively high storage requirement of the buffer memory to be provided. For memory devices with an in-built self-testing unit, such a solution is usually too complex.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory which overcomes the above-mentioned disadvantageous of the prior art semiconductor memories of this general type. More specifically, an object is to provide a semiconductor memory that can be subjected to a memory cell test, wherein the semiconductor memory has a memory unit for storing addresses of defective memory cells, and wherein the storage requirement of the memory unit is as small as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention an integrated semiconductor memory which has, along with addressable normal memory cells, addressable redundant memory cells for replacing one of the normal memory cells. Furthermore, the memory has a memory unit for storing addresses of defective normal memory cells. The memory unit has a control input for controlling the storing operation of the memory unit and an output for outputting the memory content. A preprocessing device has a memory device for storing a fixed number of addresses of defective normal memory cells. It serves for the comparison between the stored addresses and the outputting of an output signal according to the result of the comparison. The preprocessing device has, furthermore, an output for the outputting of the output signal, which is connected to the control input of the memory unit. With a circuit configuration of this type, in which defect information is buffer-stored in the memory unit in the course of a memory test, the size of the memory unit can be kept small.
The size of the memory unit is kept small because the defect information irrelevant to the repair phase following the test has already been filtered out by the preprocessing device during the buffer storage in the memory unit. This irrelevant information is no longer stored. The comparison carried out for this purpose between the defect addresses stored in the preprocessing device takes place in a suitable way with regard to which of the normal memory cells are to be replaced by which of the redundant memory cells. There consequently takes place a kind of preprocessing of the defect information, present in the form of addresses of defective memory cells, with regard to the subsequent redundancy analysis.
In accordance with an added feature of the invention, the addresses of memory cells which are configured in a memory cell array in matrix form and are combined into addressable units of column lines and row lines have, for example, a first address part, via which the respective column line is accessed, and a second address part, via which the respective row line is accessed. Accordingly, the memory device of the preprocessing device has, for example, register units for the storing of in each case one of the address parts, which are connected to each other in the form of a shift register.
In accordance with an additional feature of the invention, the outputs of the register units are connected to corresponding inputs of a comparison device for a comparison between the contents of the register units. An output of the comparison device is connected to the output of the preprocessing device and consequently to the contro
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Tan T.
Stemer Werner H.
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