Integrated semiconductor memory of the dram type and method for

Details Integrated semiconductor memory of the dram type and method for Integrated semiconductor memory of the dram type and method for

1990-03-15

1993-02-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365203, 365149, G11C 700

Patent

active

051843269

ABSTRACT:
An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.

REFERENCES:
patent: 4799196 (1989-01-01), Takemae
Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, Shozo Saito et al: A 1-Mbit "CMOS DRAM with Fast Page Mode and Static Column Mode", pp. 903-908.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, Katsutaka Kimura et al: "A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sense Amplifier", pp. 651-656.
1984 IEEE International Solid-State Circuits Conference, ISSCC 84/Friday, Feb. 24, 1984, Session XVIII: 256K/1Mb DRAMs-II; Roger I. Kung et al: "FAM 18.4: A Sub 100ns 256K DRAM in CMOS III Technology"; pp. 278, 279, 354.
IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978, R. H. Linton "Technique For Optimizing Signals in Dynamic Memory Systems", pp. 4297, 4298.
IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978 R. H. Linton "Memory Noise Compensation Network", pp. 4299, 4300.

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