Integrated semiconductor memory devices with generation of...

Details Integrated semiconductor memory devices with generation of... Integrated semiconductor memory devices with generation of...

2007-02-01

2008-10-28

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189080, C365S233110, C365S233120

Reexamination Certificate

active

07443739

ABSTRACT:
An integrated semiconductor memory device includes a clock terminal that applies an external clock signal. Read and write accesses are controlled synchronously with the external clock signal. A frequency detector is connected to the clock terminal to detect the frequency of the external clock signal. The frequency detector circuit generates a control signal in a manner dependent on the frequency of the external clock signal, the control signal being used to drive a controllable voltage generator, which generates a level of an internal supply voltage in a manner dependent on the control signal, from which supply voltage further control and supply voltages are derived. The integrated semiconductor memory device makes it possible to adapt the level of internally generated voltages of the integrated semiconductor memory device to the frequency of the external clock signal.

REFERENCES:
patent: 6055210 (2000-04-01), Setogawa
patent: 6094395 (2000-07-01), Weinfurtner
patent: 6661728 (2003-12-01), Tomita et al.
patent: 2005/0270890 (2005-12-01), Kim
patent: 2006/0238216 (2006-10-01), Yada et al.
patent: 2007/0253125 (2007-11-01), Kuroda
patent: 2007/0268777 (2007-11-01), Brox
patent: 2008/0116950 (2008-05-01), Baek et al.

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