Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-01-30
2007-01-30
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S189120, C365S194000, C365S236000
Reexamination Certificate
active
11121171
ABSTRACT:
A semiconductor memory includes a control circuit for generating an internal read command signal depending on an externally applied read command signal. A clock generating circuit generates a system clock signal and a time shifted clock signal generated by a DLL circuit. A latency counter circuit comprises a first control circuit for generating a first control signal and a second control circuit for generating a second control signal. The first control signal is used to latch the internal read command signal in one of FIFO-latching cells. The latching is carried out in a system clock domain. The second control signal is used to release a time shifted internal read command signal from one of the FIFO-latching cells in a DLL clock domain. The relationship between first and second control signals determines a CAS latency by which data items appear at a data terminal synchronous with an externally applied clock signal.
REFERENCES:
patent: 5517462 (1996-05-01), Iwamoto et al.
patent: 6075393 (2000-06-01), Tomita et al.
patent: 6636110 (2003-10-01), Ooishi et al.
Dinh Son T.
Edell Shapiro & Finnan LLC
Infineon - Technologies AG
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