Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-30
2003-09-30
Hu, Shouxiang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S303000, C257S308000, C257S621000
Reexamination Certificate
active
06627934
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention:
The invention relates to an integrated semiconductor memory configuration having a plurality of identical memory cells.
Each of the memory cells has a selection transistor having a drain region, a source region, and a gate. A storage capacitor of the memory cell has a first electrode, a second electrode and also a storage dielectric provided between the two electrodes.
The invention further relates to a method of fabricating an integrated semiconductor memory configuration having a plurality of identical memory cells.
In the case of a memory configuration of this type, additional space for interconnection or wiring is available on a main surface of the insulation layer above the selection transistors.
A memory configuration of this general type is disclosed in the German Published Patent Application DE 38 40 559 A1. The memory configuration described therein has a storage capacitor which is provided below a source region. The storage capacitor is conductively connected to the source region by a first electrode. A second electrode of the storage capacitor is connected to a common plate provided below the source region.
The German Published Patent Application DE 39 31 381 A1 describes a memory configuration having switching elements provided in a substrate below selection transistors. These switching elements may be embodied e.g. as storage capacitors connected by a first electrode to a source region of a selection transistor and by a second electrode to a common plate embodied as a buried interconnection plane.
The U.S. Pat. No. 4,794,434 discloses a memory configuration having a number of selection transistors whose respective source region is connected to a first electrode of a storage capacitor. The storage capacitor is situated in a substrate below the source region, and the second electrode below the source region is formed by a conductive substrate region which is electrically insulated from the source region.
The U.S. Pat. No. 5,309,008 describes a memory configuration having a number of selection transistors each having a source region which is connected to a first electrode of a storage capacitor. The storage capacitors are situated in a substrate in which also the source regions are provided. A second electrode of the storage capacitors is connected to a common plate provided below the source regions.
A disadvantage of the conventional memory configurations is the spatial configuration of the storage capacitors, which have to be fabricated prior to the selection transistors in the course of the production process. Particularly when special storage dielectrics, such as ferroelectric storage dielectrics, are used, contamination of the semiconductor process employed for fabricating the selection transistors can occur as a result of using these storage dielectrics.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory configuration, which overcomes the abovementioned disadvantages of the heretofore-known semiconductor memory configurations of this general type and in which additional space is available for interconnections on a main surface of the memory configuration, and which furthermore can easily be fabricated using conventional method steps.
A further object of the invention is to provide a method for fabricating the semiconductor memory configuration according to the invention.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory configuration, comprising:
a) a semiconductor body having a first side and a second side;
b) an insulation layer formed on the first side of the semiconductor body, the insulation layer having a cutout formed therein, the cutout having a side surface;
c) a common plate formed on the second side of the semiconductor body; and
d) a memory cell including
a selection transistor having a drain region formed in the semiconductor body, a source region formed in the semiconductor body and disposed between the cutout in the insulation layer and the common plate, and a gate formed in the insulation layer;
a storage capacitor provided on the side surface of the cutout, the storage capacitor having a first electrode connected to the source region of the selection transistor, a second electrode connected to the common plate, and a storage dielectric disposed between the first electrode and the second electrode.
In accordance with another feature of the invention, the storage dielectric has ferroelectric properties.
In accordance with yet another feature of the invention, the storage dielectric has a dielectric constant of greater than 10.
In accordance with a further feature of the invention, the storage dielectric is an oxidic dielectric and in particular SBTN SrBi
2
(Ta
1−x
Nb
x
)
2
O
9
, SBT SrBi
2
Ta
2
O
9
, PZT (Pb, Zr) TiO
3
, BST (Ba, Sr)TiO
3
, or ST SrTiO
3
.
In accordance with another feature of the invention, the cutout is formed centrally over the source region.
In accordance with yet another feature of the invention, a conductive connection element extends downward through the source region and the semiconductor body and connects the second electrode to the common plate.
In accordance with a further feature of the invention, the storage dielectric extends downward through the source region and the semiconductor body to the common plate and surrounds the conductive connection element.
In accordance with another feature of the invention, the storage dielectric and the second electrode extend downward through the source region and the semiconductor body to the common plate and enclose the conductive connection element.
In accordance with yet another feature of the invention, an insulation collar extends downward through the source region and the semiconductor body to the common plate and encloses the conductive connection element in a region of the source region and in a region of the semiconductor body.
In accordance with another feature of the invention, the common plate and the semiconductor body form an integral semiconductor substrate, the common plate being a doped region of the semiconductor substrate.
With the objects of the invention in view, there is also provided a method of fabricating a semiconductor memory configuration, the method which comprises:
providing a semiconductor body having a first side and a second side;
providing an insulation layer on the first side of the semiconductor body;
fabricating a common plate on the second side of the semiconductor body;
doping the semiconductor body for forming a source region and a drain region of a selection transistors;
providing a gate for the selection transistor in the insulation layer;
etching the insulation layer for forming a first cutout in the insulation layer over the source region;
applying a first electrode on a side surface of the first cutout;
further etching the first cutout through the source region and the semiconductor body as far as to the common plate for forming a second cutout;
depositing a storage dielectric and a second electrode on the first electrode and on a side surface of the second cutout; and
filling an interspace within the second electrode with conductive material for fabricating a conductive connection element.
With the objects of the invention in view there is furthermore provided a method of fabricating a semiconductor memory configuration, the method which comprises:
providing a semiconductor body having a first side and a second side;
providing an insulation layer on the first side of the semiconductor body;
fabricating a common plate on the second side of the semiconductor body;
doping the semiconductor body for forming a source region and a drain region of a selection transistor;
providing a gate for the selection transistor in the insulation layer;
etching the insulation layer for forming a first cutout in the insulation layer over the source region;
applying a first electrode on a side surface of the first cutout;
depositing a storage dielectric and a seco
Mazure-Espejo Carlos
Schindler Günther
Greenberg Laurence A.
Hu Shouxiang
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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