Integrated semiconductor memory circuit and a method for...

Details Integrated semiconductor memory circuit and a method for... Integrated semiconductor memory circuit and a method for...

2005-11-15

2005-11-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000, C365S185130

Reexamination Certificate

active

06965535

ABSTRACT:
An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.

REFERENCES:
patent: 5546349 (1996-08-01), Watanabe et al.
patent: 5715209 (1998-02-01), Yoo
patent: 5822268 (1998-10-01), Kirihata
patent: 6163501 (2000-12-01), Ohshima et al.

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