Integrated semiconductor memory array having improved logic latc

Details Integrated semiconductor memory array having improved logic latc Integrated semiconductor memory array having improved logic latc

1978-10-16

1979-11-20

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 365181, 307238, G11C 1140

Patent

active

041752902

ABSTRACT:
There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state. Therefore, if power is removed and then returned, the latch will always settle into a state dictated by the final state that existed in the latch before the high voltage pulse was applied. In this way the variable threshold elements of the latch cell make it a non-volatile memory element. It can be used either as a read/write memory, using its latch property, or as a read-only memory, using the variable threshold transistors to cause it to always latch in a predetermined manner.

REFERENCES:
patent: 3882467 (1975-05-01), Pricer
patent: 4095281 (1978-06-01), Denes

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