Integrated semiconductor memory and method for operating a...

Static information storage and retrieval – Read/write circuit – Complementing/balancing

Reexamination Certificate

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C365S203000

Reexamination Certificate

active

07813196

ABSTRACT:
An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair coupled to at least one of the multiplicity of bit line pairs for outputting a datum is furthermore provided. A correction device is connected on the output side to the data line pair or to at least one bit line pair. The device is embodied for feeding a correction signal onto the line pair.

REFERENCES:
patent: 4404660 (1983-09-01), Menachem
patent: 6343038 (2002-01-01), Makino et al.
patent: 6545922 (2003-04-01), Nakazawa

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