Integrated semiconductor memory

Details Integrated semiconductor memory Integrated semiconductor memory

1991-07-26

1993-10-12

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365149, 365203, G11C 2900

Patent

active

052532097

ABSTRACT:
An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

REFERENCES:
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4885748 (1989-12-01), Hoffmann
patent: 4896322 (1990-01-01), Kraus
patent: 4920515 (1990-04-01), Obata
patent: 4999813 (1991-03-01), Ohtsuka

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