Integrated semiconductor memory

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S225700, C365S239000

Reexamination Certificate

active

11234383

ABSTRACT:
An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.

REFERENCES:
patent: 6208567 (2001-03-01), Yamauchi et al.
patent: 6246627 (2001-06-01), Yamauchi et al.
patent: 3924695 (1990-02-01), None

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