Integrated semiconductor memory

Details Integrated semiconductor memory Integrated semiconductor memory

1985-12-20

1988-05-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

371 21, G11C 700

Patent

active

047424893

ABSTRACT:
An integrated semiconductor memory includes n identical memory cell fields each having a data width equal to m, n.multidot.m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators for applying the memory data as a function of addressing data when written-in, m second data separators for selecting one of the n data lines in response to the addressing data. It further has evaluation circuits connected to n of the n.multidot.m data lines parallel to the respective second data separators. It also has third data separators connected between each of the m data input terminals and the n of n.multidot.m data lines parallel to the first data separators for transferring the memory data in parallel to all of the n data lines in response to the control signal, and fourth data separators each preceding a respective one of the m data output terminals for selectively feeding the memory data selected by the second data separators or the output signal generated by the evaluation circuit to the data output terminals in response to the control signal and a complementary signal.

REFERENCES:
patent: 4541090 (1985-09-01), Shiragasawa
S. Eaton et al., "A 100ns 64K Dynamic RAM Using Redundancy Techniques", IEEE International Solid-State Circuits Conference--Digest of Technical Papers, Feb. 18, 1981, pp. 84-85.
P. Mattos et al., "Nibble-Mode Beschleunigt Speicherzugriff", Elektronik, No. 15, Jul. 30, 1982, pp. 27-30.

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