Integrated semiconductor-magnetic random access memory system

Static information storage and retrieval – Systems using particular element – Magnetoresistive

Reexamination Certificate

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Details

C365S171000

Reexamination Certificate

active

06219273

ABSTRACT:

BACKGROUND
The present specification generally relates to memory devices. More particularly, the present specification describes an integrated semiconductor-magnetic random access memory.
A demand for increase in data processing rate has led to search for faster and denser random access memory (RAM). Semiconductor memories such as dynamic RAM and static RAM have very fast access times but are also volatile. Electrically erasable read only memories (EPROM) are non-volatile but have very long write times and offer a conflict between refresh needs and radiation tolerance.
The concept of using magnetic material for a non-volatile RAM has been implemented before, e.g., in core memory and in magnetic RAM. A non-volatile magnetic random access memory is described in U.S. Pat. No. 5,289,410, the disclosure of which is herein incorporated by reference to the extent necessary for understanding.
SUMMARY
The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses a CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.
According to the present disclosure, magnetic storage array cells have certain hysteresis characteristic that allows data to be written to or read from the cell accurately without interference from surrounding cells. Semiconductor circuits operate to read data from and write data to the magnetic storage array cells by generating currents to apply electromagnetic fields to the cells. A preferred embodiment of the magnetic array cells uses magnetoresistive material.
A method for writing data to the magnetic memory array cells includes selecting cell address and applying appropriate currents to address lines.
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other embodiments and advantages will become apparent from the following description and drawings, and from the claims.


REFERENCES:
patent: 5289410 (1994-02-01), Katti et al.
patent: 5659499 (1997-08-01), Chen et al.
patent: 5946227 (1999-08-01), Naji

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