Integrated semiconductor circuit with ESD protection

Details Integrated semiconductor circuit with ESD protection Integrated semiconductor circuit with ESD protection

1994-05-04

1995-06-20

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257363, 361 58, 361 91, H01L 2906, H01L 2978

Patent

active

054263239

ABSTRACT:
An integrated semiconductor circuit includes a semiconductor substrate. At least one first and at least one second potential rail respectively carry first and second supply potentials of the semiconductor circuit during operation. At least one input signal line has at least one input signal terminal and at least one output signal line has at least one output signal terminal and at least one additional line connected to the output signal terminal. At least one first circuit portion receives and processes input signals and at least one second circuit portion develops at least one output signal of the semiconductor circuit during operation of the semiconductor circuit. A configuration for protection against overvoltages has a first protection circuit for each input signal terminal being connected between a respective input signal terminal and a respective first circuit portion, and has a second protection circuit for each output signal terminal being connected to the additional line. Each protection circuit has a field oxide transistor, a field-controlled diode and a diffusion resistor. The potential rails each have a region adjacent at least one of the protection circuits. At least one of the potential rails has a tub-shaped protection structure disposed under the region. The protection structure is disposed in the substrate and is electrically conductively connected to a respective one of the potential rails.

REFERENCES:
patent: 4893157 (1990-01-01), Miyazawa et al.
patent: 4893159 (1990-01-01), Suzuki et al.
patent: 4987465 (1991-01-01), Longcor et al.
patent: 5019883 (1991-05-01), Mori et al.
patent: 5027252 (1991-06-01), Yamamura
"A Synthesis of ESD Input Protection Scheme", Duvvury et al., 1991 EOS/ESD Symposium Proceedings, pp. 88-97.
"ESD Protection: Design and Layout Issues for VLSI Circuits", Duvvury et al., 1989 IEEE.

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