Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1999-06-08
2001-09-25
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S622000, C257S623000, C438S926000
Reexamination Certificate
active
06294841
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated semiconductor circuit.
As is known, integrated semiconductor circuits have what are referred to as pads, which are contact-connected to terminal pins of a housing and through which input or output signals to be processed by the semiconductor circuit are fed in or out or to which a supply potential is applied. The pads for signal input and output, in particular, are subjected to the requirement that adaptation to the connected line be performed.
By way of example, semiconductor circuits having the same circuit layout are to be connected to different bus systems. In that case, through the use of suitable circuit measures, the input/output parameters of the connections can be adapted to the desired value by suitable capacitance and resistance circuitry. If, on one hand, corresponding components outside the integrated semiconductor circuit are used for that purpose, that leads to a higher outlay for the circuit board construction and to corresponding disadvantages, e.g. an increased risk of failure. If, on the other hand, such components are realized in an integrated manner using conventional measures on the semiconductor chip, the area requirement of the circuit is increased, particularly by the realization of capacitances. A large number of process steps extending down into deeper layers of the integrated circuit are necessary in order to fabricate the integrated capacitor. Therefore, the integrated realization furthermore necessitates additional development outlay and a multiplicity of exposure masks separately assigned to each adaptation variant.
European Patent Application 0 409 256 A2 describes an integrated semiconductor circuit in which dummy structures are used to stabilize an internal supply voltage or to set a delay time for an internal signal. To that end, metal lines of the dummy structure which are not required for other purposes are connected to a supply potential line or to a signal output of a circuit block. The length of the signal line is trimmed through the use of a laser beam in order to provide the desired capacitance.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor circuit having dummy structures, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which an adaptation to input/output parameters of its connections can be carried out with a lower outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit, comprising at least one pad for inputting or outputting a signal to be processed or for feeding in a supply potential; and a dummy structure having a multiplicity of repeatedly disposed capacitive elements, at least a portion of the capacitive elements coupled to the pad; each of the capacitive elements including a comparatively recessed section of a semiconductor substrate, a comparatively elevated section of the semiconductor substrate, and a polysilicon section insulated from the recessed and elevated sections.
Dummy structures which are present anyway in the integrated circuit are used in the invention. Such dummy structures are described, for example, in U.S. Pat. Nos. 5,032,890 and 5,278,105. They are formed of regular structures which are disposed on free, unused areas of the semiconductor chip, in order to ensure a uniform process behavior of the entire circuit during fabrication, e.g. during etching, while structures are being grown, or during chemical mechanical polishing, and to obtain a uniformly level, planar surface.
Those dummy structures have had no function in electrical terms heretofore. In the invention, a portion of those dummy structures is connected to the pad in accordance with the desired input/output signal behavior and their capacitive effect is utilized. An additional area requirement does not arise. The additional process complexity lies in providing corresponding wiring, which runs in the uppermost layers of the semiconductor circuit. Therefore, only the uppermost exposure masks have to be adapted and the structures situated underneath remain unchanged.
As an alternative, fuses may also be used instead of metal wiring. Portions of the dummy structures which are combined, if appropriate, to form larger regions, are connected to the pads by the fuses. Following the mask process steps during fabrication, fuses are melted through or blown in order to trim the capacitive loading on the pad to the desired value. A multiplicity of different settings of the input/output parameters are thereby obtained in a flexible and rapid manner.
Therefore, in accordance with another feature of the invention, there are provided interruptible fuses each connecting a respective one of the capacitive elements to the pad, the fuses connecting the portion of the multiplicity of the capacitive elements to the pad not being interrupted, and remaining fuses being interrupted.
As an alternative or in combination with the above embodiments, portions of the dummy structures are coupled to the output terminal through switches, having a switching state which is set during operation of the semiconductor memory.
Therefore, in accordance with a further feature of the invention, there are provided switching elements each connecting a respective one of the capacitive elements to the pad, the switching elements connecting the portion of the multiplicity of the capacitive elements to the pad being turned on during operation of the semiconductor circuit, and remaining switching elements being turned off during the operation of the semiconductor circuit.
In accordance with an added feature of the invention, there is provided a surface area not occupied by transistors, the dummy structure disposed in the surface area, an oxide layer disposed between the substrate and the polysilicon sections, the polysilicon sections disposed above at least the recessed sections of the semiconductor substrate, and a portion of the polysilicon sections connected to the pad.
In accordance with an additional feature of the invention, the polysilicon sections have a rectangular structure and are disposed at predetermined locations in a regular grid.
In accordance with yet another feature of the invention, a neighboring plurality of the polysilicon sections are jointly connected to one another to form a region, an interruptible fuse connects the common connection of the region to a common connection of a further corresponding region, and the interruptible fuse is interrupted unless the region is connected to the pad.
In accordance with yet a further feature of the invention, each of the regions includes a number of the interconnected polysilicon sections, and different regions are spaced apart defining a grid location at which no polysilicon section is disposed lying between directly neighboring polysilicon sections in the regions.
In accordance with yet an added feature of the invention, there is provided an interconnect connecting the portion of the multiplicity of the capacitive elements to the pad, the interconnect having a section through which a predetermined resistance is set, and the fuses or the switching elements disposed between the section and the connection to the polysilicon sections.
In accordance with a concomitant feature of the invention, there is provided a plurality of sections of interconnects electrically connected in parallel and through which the same predetermined resistance is set in each case.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor circuit having dummy structures, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the clai
Feurle Robert
Savignac Dominique
Schneider Helmut
Cao Phat X.
Chaudhuri Olik
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
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