Integrated semiconductor circuit having a multiplicity of...

Details Integrated semiconductor circuit having a multiplicity of... Integrated semiconductor circuit having a multiplicity of...

2005-11-22

2005-11-22

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000

Reexamination Certificate

active

06967370

ABSTRACT:
An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitors, which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts, additional contact structures which lead past the word lines and represent dummy contacts can be provided. The additional parasitic capacitances produced by the dummy contact alter the electrical potential of the respective reference bit line at the signal amplifier like the parasitic capacitances of activated bit lines, as a result of which the measured differential potential can be corrected with respect to the parasitic effects.

REFERENCES:
patent: 6281586 (2001-08-01), Feurle et al.
patent: 6310399 (2001-10-01), Feurle et al.
patent: 2004/0196711 (2004-10-01), Vollrath et al.
patent: 2004/0201051 (2004-10-01), Schroder et al.

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