Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-17
2004-01-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06681376
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an integrated scheme for semiconductor devices verification.
Markets for memory-based products are explosively growing in the recent years. This growth makes it necessary to reduce development cycle time and increase fabrication facility throughput. As devices shrink with each succeeding generation, and standard cell libraries continuously grow to accommodate increasingly more complex applications, the layouts become extremely dense. High layout density is also required for all the cells adjacent to the memory core, in order to preserve the pitch of interconnecting lines.
In order to expedite new product introduction, manufacturability of the various cells often needs to be analyzed based on optical and device simulations. Such simulations, however, have not been adequately integrated and have not been able to predict complex issues related to design performance.
In a standard product design flow, the first step to verify manufacturability is a design rule check (DRC), based on the inputs from technology development and implemented by CAD (computer aided design). Design rules typically verify. dependencies related to process integration, among features drawn on different layers. In addition, one can verify properties of the individual mask layers, i.e., including process related sizing, pattern enhancement features, etc. Mask layer verification has recently become supplemented by optical simulation of the photoresist pattern. However, DRC of such simulated layouts does not provide information about the manufacturability of the devices realized by the proposed layouts. Single-level simulation can provide the insight into what the difference is between the drawn (target) and the final photoresist pattern on wafer, based on the intermediate mask stage. However, it cannot demonstrate how critical the difference could be between the drawn and final features, especially for MOSFET channels and contact areas.
BRIEF SUMMARY
In a first aspect, the present invention is a method for determining device yield of a semiconductor device design, comprising determining statistics of at least one device parameter from at least two device layer patterns; and calculating device yield from the statistics. At least one of the device layer patterns is neither a diffusion layer pattern nor a gate poly layer pattern.
In a second aspect, the present invention is a method of preparing a semiconductor device, comprising determining device yield of a semiconductor device design, and producing a device corresponding to the semiconductor device design.
In a third aspect, the present invention is a computer program product on a computer readable medium, for determining device yield, comprising code in the computer readable medium for causing a computer to determine statistics of at least one device parameter from at least two device layer patterns, and code in the computer readable medium for causing a computer to calculate device yield from the statistics. At least one of said device layer patterns is neither a diffusion layer nor a gate poly layer.
In a fourth aspect, the present invention is a method of making an electronic device, comprising preparing a semiconductor device by the above method, and preparing an electronic device comprising the semiconductor device.
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U.S. patent application Ser. No. 09/753,137, filed Dec. 29, 2000, pending.
Axelrad Valery
Balasinski Artur
Karklin Linard
Cypress Semiconductor Corporation
Liu Andrea
Smith Matthew
Sonnenschein Nath & Rosenthal LLP
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