Integrated real-time performance monitoring facility

Details Integrated real-time performance monitoring facility Integrated real-time performance monitoring facility

1999-04-29

2002-10-01

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C714S044000

Reexamination Certificate

active

06460107

ABSTRACT:

BACKGROUND INFORMATION
This invention relates generally to techniques for monitoring the performance of digital integrated circuit electronics, and more particularly to monitoring the performance of a computer system having an I/O processor and multiple clock domains.
Monitoring a manufactured digital integrated circuit (IC) in real-time, i.e., while the IC is operating as part of the intended application, helps verify the performance of the functions provided by the IC to its surrounding system. This may be done with the help of logic analyzers and in-circuit emulators. The conventional logic analyzer monitors the system in real-time by sensing the external signal lines of the IC within the system. In-circuit emulators physically replace the IC and emulate its functions while simultaneously recording external signal behavior in real-time. These conventional tools are currently used by board designers, software architects, and operating system vendors to optimize the performance of the system for a particular application.
The conventional tools described above, however, do not provide access to certain internal signals of the IC which may prove to be useful for further optimizing system performance. For instance, the integrated circuit I/O processor (IOP) designed to facilitate intelligent I/O in modern computer systems is a particularly complex subsystem with multiple bus interfaces operating in different clock domains, i.e., different clock frequencies, and which may be difficult to emulate for real-time monitoring. The IOP may also have many internal signals not accessible by a logical analyzer but which could be particularly useful in optimizing the performance of the surrounding computer system. Without access to such internal IC behavior in real-time, the system developer may not be realizing the full potential of the computer system.
Another problem with the use of conventional techniques is that the logic analyzer and in-circuit emulators call for a significant amount of hardware additions and modifications to prepare the system for monitoring. This presents an additional burden to the system developer seeking to optimize a computer system for a particular application. One existing solution for monitoring the performance of a bus is the “exerciser” add-in card for Peripheral Component Interconnect (PCI) buses. Such a solution, however, requires that at least one slot on a PCI bus be dedicated to the exerciser card. This presents a problem for monitoring a system which has all of its slots occupied with other add-in cards. Also, with the exerciser card in place, the system must be configured with one fewer add-in card than originally contemplated, making the exerciser card an inefficient solution.
Therefore, there is a need for a novel technique for monitoring IC and bus operation which overcomes these disadvantages.
SUMMARY
An embodiment of the invention is directed to an integrated circuit (IC) having an internal bus, and a number of event counters coupled to the internal bus, each being responsive to one of a number of events of the internal bus. A number of registers are coupled to the event counters, each register containing a value of a respective one of the event counters. The registers are coupled to the internal bus and are accessible therefrom. An external bus is provided for receiving transactions from devices outside the IC to access the registers. An address translation unit is coupled between the internal bus and the external bus for transporting transactions therebetween.


REFERENCES:
patent: 4435759 (1984-03-01), Baum et al.
patent: 5450349 (1995-09-01), Brown, III et al.

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