Integrated programming circuitry for an electrically programmabl

Details Integrated programming circuitry for an electrically programmabl Integrated programming circuitry for an electrically programmabl

1994-12-28

1996-08-20

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518509, 36523002, G11C 700

Patent

active

055485545

ABSTRACT:
An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load circuit according to the logic state of the data signal line and to cause the inhibition of the activation of the respective programming load circuit.

REFERENCES:
patent: 4989181 (1991-01-01), Harada
patent: 5109360 (1992-04-01), Inazumi et al.
patent: 5287310 (1994-02-01), Schreck et al.
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5469391 (1995-11-01), Haraguchi

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