Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1995-08-18
1999-02-16
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711167, 365222, G06F 1318, G06F 13372, G11C 11406
Patent
active
058731148
ABSTRACT:
An integrated processor is provided with a memory control unit having refresh queue logic for refreshing dynamic random access memory (DRAM) banks during idle memory cycles. The refresh queue logic includes a queue counter and allows the refresh requests to be given a lower priority than other memory transactions until the required refresh rate is in danger of being violated. At this lower priority the refresh requests are honored and retired from a refresh queue only in the absence of other memory transactions. In the event that the refresh queue becomes full, top priority is given to the execution of a refresh request. In this case, a refresh request is honored and retired from the queue immediately after the conclusion of the current memory transaction. This queuing mechanism allows the refresh requests to be buffered until idle memory cycles are available or until absolutely necessary to prevent the violation of refresh timing constraints.
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Andrade Victor F.
Rahman Saba
Advanced Micro Devices , Inc.
Gossage Glenn
Kivlin B. Noel
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