Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-30
2001-02-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S303000, C438S585000, C438S586000, C438S587000, C438S592000, C438S595000, C438S634000
Reexamination Certificate
active
06194302
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the formation of spacers on gate structures for self aligned contact (SAC) structures for CMOS semiconductor devices.
2) Description of the Prior Art
The self aligned contact (SAC) is a powerful method used in semiconductor manufacturing to reduce chip size by shortening the separation of contact to polysilicon. This is especially true in memory products. The space used for lightly doped drain (LDD) limits the smallest size possible with SAC. Creation of a double spacer helps alleviate the conflict between LDD and SAC requirements.
U.S. Pat. No. 5,923,986(Shen) (same inventor as present invention) shows a method for a double spacer (1 full and 1 partial top spacer) for a Self aligned silicide (SALICIDE) process. This process differs from the process of the present invention that is directed to a distinctly different process/structure—a self aligned contact (SAC).
In U.S. Pat. No. 5,208,472 (Su et al.) a method of forming a SAC structure is described where a first side wall is used to define a LDD structure, and a second side wall is used to extend the oxide region at the gate edge and improve source/drain leakage property.
In U.S. Pat. No. 4,912,061 (Nasr) a method is described for fabricating a self aligned metal oxide semiconductor device using a disposable silicon nitride spacer.
U.S. Pat. No. 5,651,857(Cronin et al.) shows a top half spacer.
U.S. Pat. No. 5,879,993(Chien et al.) shows a double spacer (1 full and 1 half bottom spacer) for a contact structure.
U.S. Pat. No. 5,663,586(Lin) shows a double spacers process.
The use of spacers are important in forming SAC structures and protecting LDD near a gate which can lead to higher densities and smaller chips; however, there is a limit to which the density can be increased, particularly when the LDD and SAC requirements are in conflict. It is, therefore, the purpose of this invention to teach a means by which spacers can be used without the conflicting requirements of the lightly doped drain and the self aligned contact. It is also a purpose of the invention to teach a means that the gate structure can be protected by a top spacer etch buffer so that the SAC opening etch will not create shorts to the gate structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a wide top spacer for a self aligned contact (SAC) process that prevents the top comer of spacers during the contact opening etch.
It is an object of the present invention to provide a “one and a half” spacer process to form a “wide top spacer” that acts as an etch buffer to protect the top of the first spacer during a self aligned contact (SAC) opening etch.
The invention provides a method of fabrication of spacers on a gate structure for a self aligned contact (SAC) process. The method begins by providing at least two spaced gate structures on a substrate. The gate structures having a top and sidewalls. We form first spacers on the sidewalls of the gate structures. The first spacers have sidewalls. Next, we form a first insulating layer over the substrate. The sidewalls of the first spacer having a upper area above the level of the first insulating layer. Then we form a first dielectric layer over the gate structures, the first spacer and the first insulating layer. The first dielectric layer is etched back to form an top spacer on the sidewalls of the first spacer. The first spacer and the top spacer comprise a wide top spacer. We form a second insulating layer over the first insulating layer, the top spacer and the gate structures. We form a photoresist layer over the second insulating layer. The photoresist layer having a contact photoresist opening over the top spacers and first spacers. We etch the first and second insulating layers using the first and the second spacers as etch masks to form a self aligned contact (SAC) opening. Lastly, a self aligned contact (SAC) is formed filling the self aligned contact (SAC) opening.
The method uses spacers formed from two dielectric layers on the edge of the gate structure. The second spacer (top spacer) is formed on the upper shoulder of the first spacer. The top spacer functions as an etch buffer to protect the first spacer and gate structure from overetching during the etching of the SAC opening.
Another important feature of the invention is the gate cap layer and the top spacer
30
. This gate cap layer
20
along with the top spacer prevents the SAC opening etch from harming the conductive layer
16
of the gate structure. The top spacer
30
must have a high etch selectivity with respect to the second insulating layer
38
. Therefore the top spacer is composed of silicon nitride (SiN), not oxide or Silicon oxynitride.
This invention allows narrower spacers for the SAC area and a wider top spacer for the SAC opening Etch. The SAC contact area is not limited by the prior art's full length double spacers. The SAC contact can be shrunk without impacting the transistor and the technique is easily applied to either SRAM's or DRAM's or other devices.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4912061 (1990-03-01), Nasr
patent: 5208472 (1993-05-01), Su et al.
patent: 5651857 (1997-07-01), Cronin et al.
patent: 5663586 (1997-09-01), Lin
patent: 5879993 (1999-03-01), Chien et al.
patent: 5923986 (1999-07-01), Shen
patent: 6033981 (2000-03-01), Lee et al.
Ackerman Stephen B.
Nguyen Ha Tran
Niebling John F.
Saile George O.
Stoffel William J.
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