Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-25
2003-09-30
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06629291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits generally, and more specifically, to a system and method for designing and providing an integrated power solution to meet the low-power demand of system on chip (or SOC) designs.
2. Discussion of the Prior Art
The driving forces behind the system on chip integration are the constant striving for smaller package area, lower system power and lower product cost. Especially for the handheld products, for example, cell phones, pagers, global positioning systems (GPS), personal digital assistance (PDAs), laptops and palm computers are all heading in that direction. In other words, a system which used to be built on a board with a package containing several chips, bulky, short battery life, now due to SOC design, becomes a single chip package operated at low-power. Depending on the advancement of the technology, material, design tools, and testing and characterization techniques, the degree of integration, only becomes more and more sophisticated.
For example, in a conventional DRAM chip, for example, an on-chip DC generator system is necessary in order to provide many different voltage levels to effectively achieve DRAM performance. These include a Vpp pump system to provide Ivpp current for a boosted wordline operation to enhance DRAM access time; a Vbb pump system to bias the body of the transfer devices of the memory array so that the sub-threshold leakage of the cell is minimized; a Vwll pump system to hold al the unselected wordlines to a level below ground, so that the sub-threshold leakage of the array devices can be suppressed, also used to improve cell retention time. Also, in the DC generator system, there are many other voltage supplies, for example, Vbgr, a bandgap reference voltage, which is a constant voltage level insensitive to the supply voltage and temperature is used to provide reference for other circuit components; a Vrefdc voltage level varies with the supply voltage can be used for generators so that generated voltage level will vary proportional to the supply voltage; and Vcmn is a constant current reference can be used to bias certain differential amplifiers, etc.
Currently, these complicated systems comprise power system designs implementing off-chip discrete power supplies, or on-chip scattered dc supplies. In short, the DC generator system designed and fabricated in a DRAM chip is a mini-model of an integrated power supply system, which eliminates the need of providing several different voltage levels from external sources.
It is obvious that such an on-chip power supply has many advantages over the off-chip supply. For example, reduced IR drop on the supply voltages, quicker response time and thus less voltage ringing/rippling effect, power saving, etc. More importantly, no discrete power supplies are needed for each macro which means lower system cost, and better reliability. Not only DRAM has an on-chip generator system, Flash memory, microprocessor, and other semiconductor chips are all equipped with similar on-chip generators. Therefore, when placing system, or multi-macros on a chip, the most obvious approach will be each macro carries its own generator block. However, the drawbacks of this approach are: 1) the distributed DC generator (inside each macro) is not an area and power efficient design; for example, in a CPU macro, its internal supply voltage of 1.8V can also be shared for other macros, such as DRAM, SRAM, Flash memory, etc.; 2) the distributed DC generator design is less reliable. Any generator inside the macro must be kept in a good working condition. That is, in the event one of them failed to work, the whole chip may not function properly; 3) the distributed DC power system offers less design flexibility; for example, in a Flash memory, a high positive (or negative) voltage supply is needed for programming (or erasing) purposes. The conventional design obviously implements a multiple stage pump to raise the voltage from an externally provided power supply. This multiple stage pump is bulky and is used for, one purpose, either programming or erasing data to/from flash memory. However, as the flash memory is predominantly used for read operations, this pump remains mostly idle; 4) noise immunity in the distributed DC design is compromised as isolation structures must be provided for all active DC power circuitry (e.g., oscillators, charge pumps, switch capacitors); and 5) provision of the DC power system in the DRAM and Flash memory macro compromises memory array efficiency which is defined as the ratio of memory array size over the total macro size. If DC block is removed from DRAM and Flash memory macro, the array efficiency will naturally be improved.
In view of the aforementioned drawbacks, it would be highly desirable to provide a centralized, integrated power solution for low-power, low-cost and high performance multi-system on chip (SOC) designs.
It would additionally be highly desirable to provide a reliable SOC DC power supply design solution that is flexible, achieves greater chip area reduction and is power and area efficient for meeting the low-power and low cost demand of system on chip designs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a centralized high power and area efficient DC generator system for a multi-system chip (or system-on-chip, or SOC).
It is a further object of the present invention to provide a centralized high power and area efficient DC generator system in a strategic area of an SOC that includes a noise blocking structure surrounding all DC generator components which are located in that strategic area.
It is another object of the present invention to provide a centralized high power and area efficient DC generator system design for a SOC that implements sharing of a DC unit by macros so that power demand is optimized at the system level rather than from each individual macro level.
It is still another object of the present invention to provide a centralized high power and area efficient DC generator system design for a SOC such that, during power on, each DC generator syb-system is activated in a sequential way to avoid undesirable stress on the devices, and a possibility of latch-up situation.
According to the principles of the invention there is provided a centralized power supply system for a multi-system on chip device comprising: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. An effective noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.
As it is important that the accuracy of power supply levels for normal operations is ensured, the centralized high power and area efficient DC generator system design for a SOC may include an intelligent built-in-self-test (or BIST) circuit to perform a power-on test on the DC generator system to ensure each internal power supply level is established in the right sequence and with the targeted voltage supply value, and that its current supply capacity is within the specification. The BIST circuit is additionally able to conduct certain levels of repair by performing minor adjustments to or replacing a defective DC power supply component.
REFERENCES:
patent: 5063304 (1991-11-01), Iyengar
patent: 5300824 (1994-04-01), Iyengar
patent: 5777462 (1998-07-01), Yue
patent: 5966045 (1999-10-01), Asakura
patent: 6205079 (2001-03-01), Namekawa
patent: 6313695 (2001-11-01), Ooishi et al.
patent: 6366506 (2002-04-01), Mizuno et al.
“DC-DC Converters Deliver Better Performance for Distributed Power”, by David Morrison, Electronic Design, Jun. 12, 2000,
Houghton Russell J.
Hsu Joni C.
Hsu Louis L.
Wang Li-Kong
Liu Andrea
Smith Matthew
Trepp, Esq. Robert M.
LandOfFree
Integrated power solution for system on chip applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated power solution for system on chip applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated power solution for system on chip applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3103653