Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-28
2002-01-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C327S512000
Reexamination Certificate
active
06337503
ABSTRACT:
TECHNICAL FIELD
This invention relates to an integrated circuit structure which comprises a power circuit portion and a control circuit portion and is free from parasitic currents.
BACKGROUND OF THE INVENTION
In an integrated electronic structure including a power circuit portion, specifically a bipolar type of power device with a vertical current flow, and a control circuit portion, such as a P-type region, a parasitic PNP transistor is created between the base of the power device and the P region.
FIG. 1
shows a conventional integrated circuit
1
′ comprising a semiconductor substrate
2
′ of the N-type which is formed with a first well
3
′ of the P type provided for forming a power device, and a second well
4
′, also of the P type, comprising a control region.
In particular, where a bipolar power transistor Power is to be provided, a third well
5
′ of the N type is formed inside the first well
1
′, in which the emitter terminal for the bipolar power transistor Power can be formed. The power transistor Power will have its collector terminal in the semiconductor substrate
2
′ and its base terminal in the first well
3
′.
A fourth wall
6
′, also of the N type, is likewise formed inside the second well
4
′ and may be connected to a supply voltage reference Vcc, for example.
Consequently, the integrated circuit
1
′ will include a first parasitic transistor P
1
, whose emitter terminal is coincident with the base terminal of the bipolar transistor Power, i.e., with the first well
3
′. The base terminal of this parasitic transistor is coincident with the collector terminal of the bipolar power transistor Power, i.e., with the semiconductor substrate
2
′, and its collector terminal is coincident with the second well
4
′ facing the bipolar power transistor Power.
In order for the first parasitic transistor P
1
to be turned off, the value of the potential applied to its base terminal must be at least equal to, or higher than, the value of the potential applied to its emitter terminal.
This condition is always met when the power device Power is operated in the linear range. But in most applications, the power device Power will be operated actually in the saturation range, since it is to serve a switching function.
Under this operating condition, the base-collector junction of the bipolar power transistor Power, and hence the emitter-base junction of the first parasitic transistor P
1
, would be forward biased.
There practically occurs a current injection from the first well
3
′, where the power transistor is formed, to the second well
4
′. The value of this current is a function of the gain of the first parasitic transistor P
1
.
The appearance of this current in the second well
4
′ causes malfunctioning, of the control logic of the integrated circuit
1
′. For the integrated circuit
1
′ to operate correctly, it is necessary that the potential at the second well
4
′ be lower than, or equal to, the potential at the semiconductor substrate
2
′ in which the bipolar power transistor Power and control circuit portion are both formed. It is only by meeting this restriction on potentials that the turning on of a second parasitic transistor P
2
, having its base terminal coincident with the second well
4
′, emitter terminal coincident with the semiconductor substrate
2
′, and collector terminal coincident with the fourth well
6
′, can be prevented.
It should be considered, in particular, that the second well
4
′ is essentially biased to a reference value Visas through a resistive path which is represented by a resistive element R
1
. The injected current from the turning on of the first parasitic transistor P
1
obeys the following relation;
Vbias+R
1
*I−V(2)=VbeP
2
(1)
where,
Vbias is the bias voltage of the second well
4
′;
R
1
is the resistance of the resistive path inside the second well
4
′;
I is the current injected into the second well
4
′ from the turning on of the first parasitic transistor P
1
;
V(2) is the value of the potential applied to the semiconductor substrate
2
′; and
VbeP
2
is the base-emitter voltage of the second parasitic transistor P
2
;
the parasitic transistor P
2
is turned on, causing malfunction to occur in the control region of the integrated circuit.
A first known technical solution to the problem posed by the presence of parasitic transistors provides for that area of the semiconductor substrate
2
′ that lies intermediate between the first well
3
′ and the second
4
′ to be doped more heavily. In this way, the gain of the first parasitic transistor P
1
is reduced.
However, this doping must not be carried too far, if the integrated circuit
1
′ is to be held at the correct voltage. In addition, the flow of current between the wells of the P type is reduced but not eliminated, with this solution.
A second solution provides for increased spacing of the P-wells. However, not even this solution ig effective to suppress the flow of current brought about by the turning on of parasitic transistors.
A third solution provides for an intermediate region
7
′, also of the P type, to be included between the aforementioned P-wells, as shown schematically in FIG.
2
.
Unfortunately, this solution also has several drawbacks:
First, where the intermediate region
7
′ is a floating region, a self-biasing of the intermediate region
7
′ to the value of potential of the first well
3
′ is precipitated upon a parasitic PNP transistor P
1
′, associated with the well
3
′ and the intermediate region
7
′, entering its saturation range. As a result, an additional parasitic transistor P
1
″, associated with the second well
4
′ and tho region
7
′, is caused to move into its conduction range. The net effect of providing this intermediate region
7
′ is one of lowering the current gain of the parasitic elements as a whole: the net effect of the parasitic components is split between the two transistors, P
1
′ and P
1
″, but one (P
1
′) of them will be in its saturation range.
Second, when the intermediate reio
7
′ is connected to a voltage reference, e.g., to ground, and by reason of the application involved the second well
4
′ is biased to a potential level below ground, the parasitc transistor P
1
″ will move into its conduction range and draw current from the ground reference terminal to the second well
4
′.
Therefore the prior art does not adequately solve the problems of parasitic flow of current in these types of integrated circuits due to parasitic components.
SUMMARY OF THE INVENTION
Presented is an integrated circuit comprising a power device and a control region that has structural and functional features that eliminates the parasitic flow of current. The circuit is formed on a semiconductor substrate with conductivity of a first type, and incorporates a first circuit portion incorporated in a first well that includes at least one power transistor. The circuit also has a control circuit portion incorporated in a second well, and an intermediate region located between the first and second circuit portions. The conductivity of the first well, second well, and intermediate region are all of a second type. The intermediate region between the wells is biased as a function of the potential of the well wherein the power device is formed.
The features and advantages of an integrated circuit structure according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5550701 (1996-08-01), Nadd et al.
patent: 5612562 (1997-03-01), Siaudeau et al.
patent: 5729040 (1998-03-01), Sano
patent: 5763934 (1998-06-01), Aiello et al.
patent: 0 512 605 (1992-11-01), None
patent: 0 703 620 (19
Ianucci Robert
Nelms David
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Vu David
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