Integrated polysilicon diode contact for gain memory cells

Details Integrated polysilicon diode contact for gain memory cells Integrated polysilicon diode contact for gain memory cells

1995-10-27

1998-01-20

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257367, 257377, H01L 2976

Patent

active

057104484

ABSTRACT:
An integrated polysilicon diode contact having multiple doped layers. A first highly doped layer of a first dopant type is deposited on a silicon substrate. A second highly doped layer of a second, different dopant type is deposited on the substrate, separated by a spacer from the first highly doped layer. A third lower doped layer of the second dopant type is deposited on the first highly doped layer and second highly doped layers, the third lower doped layer forming a p-n junction with a source region having a dopant of the first type.

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Edward Hackbarth and Denny Duna-Lee Tang, Inherent and Stress-Induced Leakage in Heavily Doped Silicon Junction, Dec., 1988, IEE Transactions on Electron Devices, vol. 35, No. 12, Dec. 1988.
W.H. Krautschneider, et al, Fully Scalable Gain Memory Cell for Future Drams, 1991, Microelectronic Engineering, vol. 15, 1991.

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