Abrading – Machine – Combined
Reexamination Certificate
2001-12-26
2004-01-13
Hail, III, Joseph J. (Department: 3723)
Abrading
Machine
Combined
C451S005000, C451S041000, C451S056000, C451S066000, C451S285000, C451S286000, C451S287000, C451S288000, C451S289000, C451S333000, C451S443000, C451S444000, C015S077000, C015S088200, C015S088300, C015S102000
Reexamination Certificate
active
06676493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the fabrication of structures on semiconductor wafers, and more specifically to methods and apparatus of chemical mechanical planarization and associated processes.
2. Description of the Related Art
In the fabrication of semiconductor devices, integrated circuits are defined on semiconductor wafers by forming a plurality of layers over one another resulting in multilevel structures. As a result of the various layers disposed over one another, a surface topography of the wafer can become irregular, and an uncorrected irregularity increases with subsequent layers. Chemical Mechanical Planarization (CMP) has developed as a fabrication process utilized to planarize the surface of a semiconductor wafer, as well as to perform additional fabrication processes including polishing, buffing, substrate cleaning, etching processes, and the like.
At the substrate level, transistor devices having diffusion regions are formed over and into silicon substrates. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level there is a need to planarize metal or associated dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization, e.g., such as copper.
The planarization of copper metallization line patterns presents particular challenges in semiconductor wafer manufacture. Metal CMP operations are typically utilized to remove excess copper, or other metal, deposited over a substrate having features formed therein. The excess copper is removed from the surface of the substrate leaving only the features filled with copper. The differing types of materials, densities of materials, and the like at the surface of the substrate, respond to CMP differently, and can result in varying removal rates and overpolishing. In the fabrication of copper dual damascene structures, non-uniform and variable materials require precision CMP with maximum control of the process and without overpolish.
Methods and processes used in the fabrication of, by way of example, copper dual damascene and LowK dielectric structures are evolving over prior art, but CMP processes remain integral to the fabrication process. What is needed are apparatus and methods to consolidate and integrate the most technologically advanced CMP process operations with closely related substrate cleaning and drying operations. The apparatus and methods should be implemented in such a manner as to maintain efficient and economical manufacturing practices and facilities, and high through-put of processed semiconductor wafers.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an integrated processing system that integrates CMP, scrubbing and cleaning, and spin-rinse-dry operations in a single cluster tool environment. The present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, and a method. Several embodiments of the present invention are described below.
In one embodiment, a wafer processing module is disclosed. The wafer processing module includes a pad magazine for holding CMP pads. A pad spindle having a pad carrier is provided and configured to connect to one of the CMP pads. Also provided is a pad exchange robot for accessing CMP pads in the pad magazine, and positioning CMP pads for connecting to the pad carrier. A wafer carrier on a wafer spindle is configured to hold a wafer to be processed, and the pad carrier is partially positioned over the wafer carrier for sub-aperture processing of the wafer.
In another embodiment, a dual wafer processing module is disclosed. The dual wafer processing module includes a pair of pad magazines for holding CMP pads. A first wafer carrier for holding wafers to be processed is configured to a first wafer spindle, and the first wafer spindle and carrier are aligned with one of the pair of pad magazines. A second wafer carrier for holding wafers to be processed is configured to a second wafer spindle, and the second wafer carrier and spindle are aligned with another one of the pair of pad magazines. The dual wafer processing module further includes a first pad spindle with a first pad carrier to which one of the CMP pads is connected, and a second pad spindle with a second pad carrier to which one of the CMP pads is connected. A pad exchange robot for accessing CMP pads held in the pair of pad magazines is also included. The pad exchange robot further positions CMP pads for connecting to the first and second pad carriers. The first pad carrier and the second pad carrier are each configured to partially apply respective CMP pads over each of the first and second wafer carriers.
In still a further embodiment, a system for processing wafers is disclosed. The system for processing wafers includes a module frame for integrating a wafer planarization unit, a wafer scrubbing unit; and an SRD unit. The integrated wafer planarization unit includes a pad magazine for holding CMP pads, and a pad spindle with a pad carrier configured to connect to one of the CMP pads. A pad exchange robot for accessing CMP pads held in the pad magazine is included which positions one of the CMP pads for connection to the pad carrier. Also included is a wafer spindle with a wafer carrier for holding a wafer to be processed. The pad carrier is capable of being partially positioned over the wafer carrier for sub-aperture processing of the wafer.
In yet another embodiment, a wafer preparation system is disclosed. The wafer preparation system includes at least one base unit that supports a sub-aperture CMP preparation system. The sub-aperture CMP preparation system is housed in and supported by the base unit. Also included is a pad exchange system to exchange CMP processing pads used in the sub-aperture CMP preparation system. The pad exchange system includes a pad exchange robot to remove CMP processing pads from, and to attach CMP processing pads to the sub-aperture CMP preparation system. The pad exchange system also obtains CMP processing pads from, and deliver CMP processing pads to a pad magazine. The pad exchange robot is attached to the base unit. The pad exchange system includes at least one pad magazine that is configured to hold a plurality of CMP processing pads for use in the sub-aperture CMP processing system. The pad magazine is attached to the base unit.
The advantages of the present invention are numerous. One notable benefit and advantage of the invention is the consolidation and integration of related fabrication processes into a single integrated system. In the fabrication of certain semiconductor structures such as LowK dielectrics and copper dual damascene structures, repeated processing through the processes of CMP, wafer cleaning, and SRD is typically required. The present invention integrates the most technologically advanced of these processing tools for precision processing, high through-put, and economy of floor space and facility support requirements.
Another benefit is the integrated pad exchange system. By implementing a pad exchange robot and pad magazine, one embodiment of the present invention maintains a constant supply and exchange of processing surfaces to maintain steady-state and consistent processing with higher operational time for integrated processing systems by eliminating the requirement for system shut-down to change pads.
REFERENCES:
patent: 5271774 (1993-12-01), Leenaars et al.
patent: 5672239 (1997-09-01), DeOrnellas
patent: 5778554 (1998-07-01), Jones
Gotkis Yehiel
Owczarz Aleksandar
Hail III Joseph J.
Lam Research Corporation
Martine & Penilla LLP
McDonald Shantese
LandOfFree
Integrated planarization and clean wafer processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated planarization and clean wafer processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated planarization and clean wafer processing system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3260457