Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-09-09
1998-08-18
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438623, 438626, 438627, 438688, 438687, 438642, H01L 2940, H01L 2348, H01L 2352
Patent
active
057958190
ABSTRACT:
A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.
REFERENCES:
patent: 3555365 (1971-01-01), Forlani et al.
patent: 3564354 (1971-02-01), Aoki et al.
patent: 4873506 (1989-10-01), Gurevich
patent: 4933303 (1990-06-01), Mo
patent: 5063175 (1991-11-01), Broadbent
patent: 5389814 (1995-02-01), Srikrishman et al.
patent: 5512514 (1996-04-01), Lee
patent: 5559367 (1996-09-01), Cohen et al.
patent: 5663590 (1997-09-01), Kapoor
J. E. Cronin et al. "Polysilicon Strap Process for Fuseszz", Kenneth Mason Publications Ltd, England, Mar. 1990, No. 311.
K. B. Albaugh et al. "Fuse Structure for Wide Fuse Materials Choice", vol. 32, No. 3A, Aug. 1989, pp. 438-439.
Geffken Robert Michael
Motsiff William Thomas
Uttecht Ronald Robert
Bowers Jr. Charles L.
International Business Machines - Corporation
Tvguyen Thanh
Walter Howard J.
LandOfFree
Integrated pad and fuse structure for planar copper metallurgy does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated pad and fuse structure for planar copper metallurgy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated pad and fuse structure for planar copper metallurgy will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1114350