Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-12-20
2003-05-27
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000
Reexamination Certificate
active
06570405
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated output driver circuits.
BACKGROUND OF THE INVENTION
Integrated circuits typically include output drivers therein for driving on-chip and off-chip loads. To reduce power (Vdd) bounce and ground (Vss) bounce problems in integrated circuits, circuit designers have developed techniques to slowly turn on the output drivers to minimize power and ground bounce effects. Such techniques typically result in a trade off between operating speed and power and ground bounce. One conventional technique for minimizing power and ground bounce in an output driver is illustrated by FIG.
1
. The output driver of
FIG. 1
includes an NMOS pull-down transistor N
2
having a drain electrically coupled to an output OUT of the driver. When the NMOS pull-down transistor N
2
is turned on, the output OUT is pulled low to Vss. When the NMOS pull-down transistor N
2
is turned off, the output OUT is disposed in a high impedance state. The gate of the NMOS pull-down transistor N
2
is controlled by a driver control circuit. This control circuit includes a totem pole arrangement of a PMOS pull-up transistor P
1
, a resistor R
1
and an NMOS pull-down transistor N
1
, connected as illustrated. A gate of the PMOS pull-up transistor P
1
and a gate of the NMOS pull-down transistor N
1
are electrically connected together and responsive to an input signal IN.
In the output driver of
FIG. 1
, the resistor R
1
is included in order to slow down the rate at which the NMOS pull-down transistor N
2
is turned on in response to a logic 0 input signal IN. The inclusion of the resistor R
1
slows down the driver by slowing down the rate at which the voltage at the gate of NMOS pull-down transistor N
2
transitions from 0 volts to Vth volts (where Vth is the threshold voltage of the NMOS pull-down transistor N
2
). However, the inclusion of the resistor R
1
does not significantly improve the ground bounce characteristics of the driver. The slow down in speed of the driver is particularly serious when Vdd is relatively low. In contrast, when Vdd is high, the sinking current provided by resistor R
1
increases and causes the voltage at the gate of the NMOS pull-down transistor N
2
to ramp up faster and this increases ground bounce. Thus, the use of a resistor makes speed slower at low Vdd and ground bounce greater at high Vdd. Moreover, at low temperature, the sinking current through resistor R
1
increases (because the resistance of resistor R
1
decreases) and the drain-to-source current through the NMOS pull-down transistor N
2
increases. This makes ground bounce worse at lower temperatures and speed slower at high temperatures. What is needed, therefore, are driver circuits having excellent ground and Vdd bounce characteristics that are at least substantially independent of changes in Vdd and temperature.
SUMMARY OF THE INVENTION
Integrated output driver circuits according to embodiments of the present invention have sourcing and sinking current characteristics that reduce power (Vdd) and ground (Vss) bounce effects by making the dl/dt characteristic of the sourcing current to a load and/or sinking current from the load more nearly uniform and substantially independent of Vdd and temperature. Improved speed characteristics can also be achieved using capacitive bootstrapping to quickly turn on an NMOS pull-down transistor, which controls the sinking current from the load, and/or PMOS pull-up transistor, which controls the sourcing current to the load.
In particular, an integrated driver circuit according to one embodiment of the present invention includes a first driver transistor and an output signal line electrically coupled to a first current carrying terminal of the first driver transistor. The first driver transistor may be an NMOS pull-down transistor having a drain connected to the output signal line and a source electrically coupled to a reference power supply line (e.g., Vss). The first driver transistor may also be a PMOS pull-up transistor having a drain connected to the output signal line and a source electrically coupled to a positive power supply line (e.g., Vdd). The driver circuit also includes a preferred driver control circuit. According to one aspect of this embodiment, the driver control circuit has a switchable pull-up path therein that extends between a gate of the first driver transistor and the positive power supply line. This switchable pull-up path includes a depletion mode transistor (NMOS or PMOS) having a first current carrying terminal electrically coupled to the gate of the first driver transistor. The depletion mode transistor may be a buried channel device. The gate and the first current carrying terminal of the depletion mode transistor are electrically connected together. The switchable pull-up path may also include a PMOS pull-up transistor having a drain electrically coupled to a second current carrying terminal of the depletion mode transistor and a source electrically coupled to the positive power supply line.
To improve speed characteristics, a bootstrap capacitor is provided having a first electrode electrically connected to the second current carrying terminal of the depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the depletion mode transistor. In particular, preferred high speed characteristics can be achieved by sizing the capacitor so that its capacitance is in a range between about 0.75 and 1.25 times C
ideal
, where C
ideal
=|Vth|(Cin)/(Vdd−|Vth|), Vth is a threshold voltage of the NMOS pull-down transistor, Cin is an input capacitance of the NMOS pull-down transistor and Vdd represents a magnitude of a power supply voltage applied to the positive power supply line. The on-state characteristics of the depletion mode transistor are also chosen so that its l
dsat
characteristic has a right positive temperature coefficient (i.e., dl
dsat
/dT is positive). The value of the positive temperature coefficient is sufficient to at least substantially compensate for a reduction in majority carrier mobility in an N-type inversion layer channel of the NMOS pull-down transistor. This reduction in majority carrier mobility occurs in response to an increase in temperature over a first operating temperature range. According to another embodiment of the present invention, the driver control circuit has a switchable pull-down path that extends between the gate of the first driver transistor and the reference power supply line. This switchable pull-down path includes a depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first driver transistor, which is preferably a PMOS pull-up transistor.
Still further embodiments of an integrated driver circuit include a first NMOS pull-down transistor and a first PMOS pull-up transistor connected together in a totem pole arrangement that extends between a positive power supply line and a reference power supply line. A gate of the first NMOS pull-down transistor and a gate of the first PMOS pull-up transistor may be connected together or independently controllable in the event a high impedance output condition is desired. A first driver control circuit is provided having a switchable pull-up path therein that extends between a gate of the first NMOS pull-down transistor and the positive power supply line. This pull-up path includes a first depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first NMOS pull-down transistor. The first depletion mode transistor may be a PMOS or NMOS depletion mode transistor having its gate and source terminals connected together. A second driver control circuit is also provided having a switchable pull-down path therein that extends between a gate of the first PMOS pull-up transistor and the reference power supply line. This pull-down path includes a second depletion mode transistor havi
Integrated Device Technology Inc.
Le Don
Myers Bigel & Sibley & Sajovec
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