Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-06-22
2003-02-25
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S225700
Reexamination Certificate
active
06525974
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated memory with redundancy.
It is generally known how to replace defective memory locations with redundant memory cells and thus repair the memory. The redundant memory locations are disposed either along redundant word lines or redundant bit lines. For example, in U.S. Pat. No. 5,568,432 an integrated memory with a redundant bit line is described, which is provided for replacing one of the normal bit lines along which normal memory locations are disposed. The normal bit line is allocated to a read amplifier, which delivers the information stored in the memory locations outside the memory in an amplified form when the memory locations are read out. The redundant bit line has a redundant read amplifier allocated to it, which serves to amplify information that is read out of the redundant memory locations in a redundancy operation, i.e. after the normal bit line has been replaced by the redundant bit line. In a redundancy operation, the defective normal bit line with its normal read amplifier is replaced by the redundant bit line with its redundant amplifier.
U.S. Pat. No. 5,761,138 teaches a semiconductor memory with a flexible redundancy block architecture. Blocks with redundant read amplifiers respectively contain four read amplifiers, which are each connected to a data line at the output side and jointly connected to a redundant global data input/data output line at an input side. Four of these respective global data input/data output lines form a bus. Redundant read amplifiers that are connected to redundant memory cell fields are connected to this, in turn. The redundancy structure serves to replace read amplifiers in memory cell fields that contain partitioned word lines and bit lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory with redundancy which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, in which data can be read over a plurality of normal read amplifiers simultaneously; in which a plurality of bit lines are allocated to each read amplifier; and in which, when defects emerge, a repair can be performed easily by redundant memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The integrated memory contains two normal read amplifiers, first switching elements having control inputs and normal bit lines combined into at least two individually addressable normal columns. At least one of the normal bit lines from each of the normal columns is connected to one of the normal read amplifiers through a respective one of the first switching elements. The control inputs of all of the first switching elements of each of the normal columns are connected to one another in order to receive a common column selection signal. Data lines are provided for transferring data to and from outside the integrated memory. At least one of the data lines is connected to one of the normal read amplifiers. The integrated memory further has two redundant read amplifiers, second switching elements having control inputs connected to one another in order to receive a common redundant column selection signal, and redundant bit lines combined into one individually addressable redundant column. At least one of the redundant bit lines is connected to one of the redundant read amplifiers through a respective one of the second switching elements. The redundant read amplifiers and the redundant column are provided for replacing the two normal read amplifiers and one of the normal columns, respectively.
The integrated memory contains two normal read amplifiers as well as normal bit lines, which are combined into at least two individually addressable normal columns. At least one of the bit lines from each normal column is connected to one of the normal read amplifiers by way of a respective first switching element. The first switching elements contain control inputs, and the control inputs of all first switching elements of every normal column are connected to one another in order to receive a common column selection signal. The memory also contains data lines for transmitting data from and to outside the memory, at least one of which is connected to one of the normal read amplifiers. It also contains two first redundant read amplifiers and first redundant bit lines combined into one individually addressable redundant column, at least one of the bit lines is connected to one of the redundant read amplifiers by way of a respective second switching element. The second switching elements contain control inputs that are connected to each other in order to receive a common redundant column selection signal. The first redundant read amplifiers and the redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.
Whereas several normal columns are allocated to the normal read amplifiers, only one redundant column having redundant bit lines is allocated to the first redundant read amplifiers. The invention is based on the recognition that, in practice, it is rare for a plurality of normal columns to contain defects. Therefore, if one were to replace all the normal columns by corresponding redundant columns given a defect in one of the normal columns, the outlay would be much greater than in the subject matter of the invention. The invention provides only one redundant column, which is sufficient for repairing defects within one normal column. In a redundancy operation, the normal read amplifiers having the defective column are replaced by the redundant read amplifiers having the redundant column; however, the normal read amplifiers continue to serve to amplify information that is read out of the remaining, non-defective normal columns.
According to a development of the invention, the integrated memory contains a second redundant read amplifier, which is connected to second redundant bit lines by way of respective third switching elements, for replacing one of the normal read amplifiers and all normal bit lines that are connected thereto by way of the first switching elements. The third switching elements have control inputs, which are provided for receiving respective additional redundant column selection signals.
The second redundant read amplifier is provided for replacing one of the normal read amplifiers including all its normal bit lines. It thus makes possible the repair of a defect that is conditioned by the read amplifier itself. Since the integrated memory according to this development contains both the first redundant read amplifiers and the second redundant read amplifiers, the utilization thereof to repair the memory depends on the type of defect. The inventive method of repairing the integrated memory thus provides that, in case of a defect of one of the normal read amplifiers, this, including the normal bit lines connected thereto, is replaced by the second redundant read amplifier and the second redundant bit lines connected thereto. In the case of a defect of one of the normal bit lines, one of the normal columns thereof is replaced by the redundant column.
According to a development of the invention, the second redundant read amplifier is connected to all the data lines by way of programmable connection elements, which are or are not electrically conductive depending on their programming status, for purposes of transferring data between one of the two redundant bit lines and one of the data lines. The connection elements make it possible to connect the second redundant read amplifier only to the data line or lines which, prior to a redundancy repair procedure, is or are connected to the normal read amplifier that has to be replaced by the second redundant read amplifier. By corresponding programming, only the connection elements which connect the second redundant read amplifier to these data lines are switched conductive. The remaining connection elements connected to the other d
Böhm Thomas
Braun Georg
Hönigschmid Heinz
Manyoki Zoltan
Neuhold Ernst
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Le Toan
Locher Ralph E.
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