Integrated memory system

Details Integrated memory system Integrated memory system

2004-03-19

2010-06-01

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S005110, C714S006130, C714S030000, C714S773000, C711S102000

Reexamination Certificate

active

07730357

ABSTRACT:
An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

REFERENCES:
patent: 5533035 (1996-07-01), Saxena et al.
patent: 5922080 (1999-07-01), Olarig
patent: 6802040 (2004-10-01), Ohyama et al.
patent: 6996741 (2006-02-01), Pittelkow et al.
patent: 7134069 (2006-11-01), Longwell et al.
patent: 2002/0069317 (2002-06-01), Chow et al.
patent: 2002/0174397 (2002-11-01), Furukawa
patent: 2003/0126513 (2003-07-01), Wuidart
patent: 2004/0015771 (2004-01-01), Lasser et al.
patent: 2001-175542 (2001-06-01), None
Null, Linda. “The Essentials of Computer Organization and Architecture.” Copyright 2003. Jones and Bartlett. pp. 73-77, 106.
European Search Report dated Sep. 23, 2003 relating to the above prior art.

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