Integrated memory having redundant units of memory cells and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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C365S200000

Reexamination Certificate

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10798334

ABSTRACT:
An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

REFERENCES:
patent: 5732029 (1998-03-01), Lee et al.
patent: 5808948 (1998-09-01), Kim et al.
patent: 5848003 (1998-12-01), Nishikawa
patent: 6349064 (2002-02-01), Nakaoka
patent: 6618306 (2003-09-01), Böhm et al.
The Authoritative Dictionary of IEEE Standards Terms, Dec. 2000, IEEE Press, 7th Edition, p. 949.

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