Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-05-30
2001-09-04
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
Reexamination Certificate
active
06285605
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having redundant units of memory cells, and a test method for its redundant units.
A memory having redundant columns is for example described in U.S. Pat. No. 4,485,459. In this case, the redundant columns are intended to replace, in terms of the respective address, a regular column of the memory. The address of the respective normal column to be replaced is stored by programmable elements in the form of interruptible electrical connections (fusible links or fuses). If the regular column to be replaced is subsequently addressed, one of the redundant columns is selected instead of the regular column to be replaced. Defects in the regular columns can thus be repaired.
It is expedient, in the case of a memory, also to test the memory cells of the redundant units (columns and/or rows of the memory) before regular units are replaced by redundant units. Otherwise, it can happen that a defective redundant unit is used when the repair is carried out. However, testing of the redundant units is made difficult by the fact that the programmable elements, which are usually embodied as fuses, can only be programmed once. They cannot, therefore, be programmed before a redundancy repair is actually carried out, in order to test the associated redundant units. On the other hand, as a rule all the redundant units are assigned programmable elements which are in the same programming state. This means that the fuses used are all intact and not interrupted. In many realizations the consequence of this is that when a specific address (e.g. the address 0) is applied, all the redundant units are addressed at once. This means that the same address in each case is assigned to these redundant units in the unprogrammed state of their programmable elements. In order to test each individual redundant unit, however, it is necessary that each redundant unit can be addressed individually. Otherwise, it is not possible to ascertain which of the tested redundant units is defective and which is not.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantages of the heretofore-known integrated memory devices of this general type and whose redundant units of memory cells can be individually addressed even in the unprogrammed state of its programmable elements assigned to the redundant units. It also an object of the invention to provide a method for testing redundant units of an integrated memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory configuration, including:
an integrated memory having memory cell configurations with normal units and redundant units, the normal units being addressable by addresses having a width of m bits, the redundant units configured for replacing respective ones of the normal units with regard to the addresses;
the redundant units having respectively assigned m programmable elements, n<m first comparison units, m-n second comparison units, a code converting unit, a logic unit, and a multiplexer, m and n being integer numbers;
the m programmable elements storing an address of one of the normal units to be replaced;
the n<m first comparison units and the m-n second comparison units having respective outputs for comparing the address stored by the programmable elements with an address of m bits fed to the integrated memory;
the code converting unit having n inputs and having n outputs, the code converting unit being supplied with n of the m bits of the address fed to the integrated memory, the code converting unit subjecting the n of the m bits to a respective type of code conversion for forming n output bits, the respective type of code conversion being different for each of the redundant units;
the logic unit having n first inputs and having m-n second inputs for performing an AND function, the logic unit generating an activation signal for a respective one of the redundant units, the second inputs of the logic unit connected to the outputs of the second comparison units; and
the multiplexer having n first multiplexer inputs, n second multiplexer inputs and n multiplexer outputs, the n multiplexer outputs being connected to the n first inputs of the logic unit, the multiplexer having a first switching state and a second switching state, the multiplexer, when being in the first switching state, connecting the outputs of the first comparison units to the first inputs of the logic unit, and the multiplexer, when being in the second switching state, connecting the outputs of the code converting unit to the first inputs of the logic unit.
In other words, in the case of the integrated memory according to the invention, the redundant units of memory cells are each assigned programmable elements for storing an address, comparison units for comparing the stored address with an address fed to the memory, a code converting unit, a logic unit for performing an AND function and a multiplexer. The code converting unit subjects n<m of the m bits of the address fed to the memory to a code conversion, the type of code conversion being different for each redundant unit. The logic unit generates an activation signal for the respective redundant unit at its output. The multiplexer has two switching states. In the first switching state, all the comparison units are connected on the output side to corresponding inputs of the logic unit. In the second switching state, only n-m of the comparison units are connected to the logic unit, while the multiplexer connects the outputs of the code converting unit to the remaining n inputs of the logic unit.
The first switching state of the multiplexers is suitable for a normal mode of the memory, in which the programmable elements are already programmed, so that the redundant units are assigned in address terms to specific normal units of memory cells. In this case, each redundant unit is assigned a different address which has been stored by its programmable elements. Consequently, when a specific address is fed in, at most one of the redundant units is selected. The second switching state of the multiplexers can nonetheless advantageously serve, in the unprogrammed state of the programmable elements, in which the latter allocate the same address in each case to the associated redundant units, for carrying out an individual addressing of the redundant units. This is necessary in particular for testing the redundant units, which has to be carried out before the programmable elements are programmed. The code converting units assigned to the redundant units ensure that respectively different n bits are fed simultaneously to the associated logic units in the second switching state of the multiplexers. Since each code converting unit carries out a different code conversion, for each address fed to the memory, at most in the case of one of the code converting units, the n bits which it generates at its output are all logic ones. Since these are subsequently fed to the AND function, at most one of the redundant units can be addressed simultaneously in the second switching state of the multiplexers.
With the objects of the invention in view there is also provided, a method for testing redundant units of an integrated memory, which includes the steps of: providing an integrated memory having memory cell configurations with normal units and redundant units, the normal units being addressable by addresses having a width of m bits, the redundant units configured for replacing respective ones of the normal units with regard to the addresses;
providing, for each of the redundant units, respective m programmable elements for storing an address of one of the normal units to be replaced;
providing, for each of the redundant units, respective n<m first comparison units and m-n second comparison units having respective outputs for comparing the address stored by the programmable elements with an address fed to the integrated memo
Dietrich Stefan
Schoniger Sabine
Schrogmeier Peter
Weis Christian
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Phan Trong
Stemer Werner H.
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