Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-06-20
2002-08-27
Mai, Son Luu (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S096000, C365S097000
Reexamination Certificate
active
06442063
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the integrated technology field and relates, more specifically, to an integrated memory having cells with a magnetoresistive memory effect. Each of the memory cells is connected between one of several column lines and one of several row lines.
Memory cells with a magnetoresistive effect generally comprise ferromagnetic layers of a modifiable condition for storing data signals. This type of memory effect is generally known as the GMR (Giant Magnetoresistive) effect or the TMR (Tunneling Magnetoresistive) effect. The electrical resistance of such a memory cell depends on the magnetization in the ferromagnetic layers.
Integrated memories having memory cells of this type—also referred to as so-called MRAM memories—are often constructed like integrated DRAM memories. Generally, these memories comprise a cell arrangement with substantially parallel row lines and column lines, whereas the row lines customarily run transverse to the column lines.
International PCT publication WO 99/14760 (corresponding to commonly assigned, copending U.S. application Ser. No. 09/528,159) describes an MRAM memory of this type. There, each of the memory cells is wired between one of the row lines and one of the column lines and electrically connected to the respective column line and row line. The memory cells with a magnetoresistive effect are thus more highly resistive than the row lines and column lines. The column lines are connected to a read amplifier for reading a data signal of one of the memory cells. Reading is accomplished by measuring the detectable current on the column line.
In an MRAM memory of that type, there are no diodes or transistors such as are provided in a DRAM memory for connecting the memory cells to the respective column lines in dependence upon the addressing for reading purposes. This brings particular advantages given a geometric arrangement of the memory cells. In particular, it is possible to save space in the arrangement of the memory cells by using a stack arrangement of the cells.
Owing to influences that are conditional to production, such as processing fluctuations, or as a result of aging, it is possible that individual memory cells may exhibit an undesirable, relatively low resistance and may thus be defective. Connected column lines and row lines are substantially shorted by way of such defective cells. Such shorts influence additional memory cells along this respective column line or row line. Furthermore, as a result of a short caused by one of the memory cells, other memory cells along affected lines can no longer be tested in a functional test. When a memory with a defective cell is repaired, the problem cannot be eliminated by replacing a single affected row line or column line, since the functioning of memory cells of the other affected line is still impaired due to the short. It is therefore necessary to replace both affected lines of a defective memory cell in this case.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a integrated memory having memory cells with magnetoresistive memory effect which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and with which the outlay for repairing the memory in the event of a defect of a memory cell which triggers a short between a row line and a column line can be reduced. with the above and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of column lines and a plurality of row lines;
a plurality of memory cells with a magnetoresisitve memory effect; and
electrical connections formed between and connecting the memory cells each to a respective one of the column lines and to a respective one of the row lines, and wherein at least one of the electrical connections is configured to be severed by a current flow through the memory cell, whereby the electrical connection is interrupted.
In other words, the object of the invention are achieved by an integrated memory with magnetoresistive memory cells that are respectively wired between one of several column lines and one of several row lines and electrically connected to the respective column line and row line. The memory cells are configured so as to be disconnectible from the respective column line and/or row line by means of a current flow through the respective memory cell, thereby interrupting the respective electrical connection.
In the inventive integrated memory, when defective memory cells emerge which trigger a short between the respective connected row line and column line, it is possible to disconnect these so as to interrupt the respective electrical connection. The short between the affected row line and column line is thus interrupted. The column line and row line connected to a defective memory cell, and the memory cells connected to these, are therefore no longer affected by the short. The column line and row line that are connected to a defective memory cell can continue to be used for a normal operation or a test operation of the integrated memory, for example. The outlay for disconnecting the memory cell is relatively small. On principle, no lines need to be replaced.
The integrated memory advantageously comprises redundant memory cells for repairing defective cells, which are combined into at least one redundant row line and/or redundant column line which can replace regular lines having defective memory cells per address. In this process, the integrated memory is tested using an external testing device, and the redundant elements are then programmed using what is known as a redundancy analysis. A redundant circuit comprises programmable elements, for instance in the form of programmable fuses, which serve for storing the address of a line that must be replaced.
To repair the integrated memory in the event of a defective memory cell, it suffices to replace only one of the affected lines by a redundant line. Since the short in the defective memory cell is interrupted, the other affected lines can continue operating. The repair outlay can be advantageously reduced in this way.
If the integrated memory comprises several redundant row lines and column lines, in the event of a defective memory cell, it is possible to proceed with a functional test of the remaining memory cells, for instance along the connected row line, if the defective memory cell is first disconnected from the affected row line. In this way, all memory cells of the integrated memory can be tested even if defective cells should meanwhile emerge. The advantage of this is that a purposeful optimized programming of the redundant lines can be carried out by means of a subsequent redundancy analysis. Since the number of redundant lines is usually limited, the production yield of integrated memories can be increased by these means.
In accordance with an added feature of the invention, the current flow for disconnecting one of the memory cells has a higher current intensity than a rated current flow for reading data signals from or for writing data signals into a respective one of the memory cells. The current flow for disconnecting a defective memory cell is, by way of example, generated by a current source that is connected from the outside. An overvoltage limit is thus expediently defined, so that a predetermined voltage is not exceeded when the elevated current is injected.
In accordance with an additional feature of the invention, electrical interconnects are respectively provided between the memory cells and each connected column line and/or between the memory cells and each connected row line. The interconnects comprise a rupture joint which can be severed by the current flow for disconnecting a defective memory cell. The rupture joint is achieved by a tapering of the width of the respective interconnect and thus forming a fuse link. The tapering is constructed such that the respective interconnect is separated by the current flow for disconnecting the d
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