Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-06-07
2001-07-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S230060
Reexamination Certificate
active
06256219
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having memory cells disposed at crossover points of word lines and bit lines.
Memories of this type include a type known as dynamic random access memories (DRAMs). The latter have sense amplifiers for amplifying data read out onto the bit lines, which are connected via switches to data lines, via which they output the amplified data to a point outside the memory. In this case, the memory cells to be addressed are selected by use of word addresses and column addresses. The word addresses serve for the selection of one of the word lines and the column addresses for the selection of at least one of the bit lines. To that end, a DRAM has a word decoder, whose outputs are connected to the word lines, and a column decoder, whose outputs are connected via column select lines to control inputs of the switches, via which the sense amplifiers are connected to the data lines. In this case, the column select lines usually run parallel to the bit lines. This is advantageous for example when a column decoder is simultaneously assigned to a plurality of memory blocks, with the result that each column select line in a plurality of the memory blocks which are adjacent in the direction of the bit lines are connected to control inputs of the switches.
Under certain circumstances, the number of column select lines may rise in such a way that it becomes problematic to accommodate them on the area that is available. This is the case, for example, when although memory blocks which are adjacent to one another in the direction of the bit lines have a common column decoder which is disposed in the direction of the bit lines at one end of the adjacent memory blocks, this common column decoder nevertheless supplies different column select signals for each of the memory blocks, which signals also have to be transmitted via different column select lines to the blocks. This is the case for example with synchronous DRAMs having a plurality of banks, where the intention is to implement so-called “bank ping-pong” (fast alternate access to a plurality of already activated memory banks). In memories of this type, the number of column select lines increases by a factor that is equal to the number of banks which share a common column decoder.
There is a minimum distance that can be achieved between the column select lines, which distance depends on the fabrication technology used. If the number of column select lines is too large, the area that is necessary for realizing the memory is no longer determined by the size of the memory cells, but by the number of column select lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory having memory cells disposed at crossover points of word lines and bit lines that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the area which is required for the column select lines running in the bit line direction is reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
bit lines;
word lines intersecting the bit lines;
memory cells disposed at crossover points of the bit lines and the word lines;
sense amplifiers connected to the bit lines for amplifying signals on the bit lines;
switching elements each having a first control input and a second control input, the switching elements are connected to the sense amplifiers;
a data line connected to the switching elements and connected through the switching element to the sense amplifiers;
first control lines running in a direction of the bit lines, the first control input of in each case two of the switching elements, which are connected to different ones of the sense amplifiers, are connected to a same one of the first control lines, and the two of the switching elements connected to the same one of the first control lines only one being electrically conductive simultaneously in a manner dependent on potentials at the second control input of each of the two of the switching elements; and
at least one second control line running in a direction of the word lines and connected to the second control input of the switching elements.
In the case of the memory according to the invention, the selection of the switching elements which connect the sense amplifiers to the data line is effected in a manner dependent on the first control lines, which run in the direction of the bit lines, and at least one second control line, which runs in the direction of the word lines. The effect advantageously achieved in this way is that the number of first control lines running in the direction of the bit lines can be reduced, thereby reducing the space that they require. In contrast, the additional presence of the second control lines running in the direction of the word lines does not constitute a significant increase in the space requirement.
According to a development of the invention, the potential of the second control lines is dependent on a bit of a column address that can be fed to the memory and serves for addressing the bit lines. Furthermore, according to the development, the integrated memory has a column decoder, to which the remaining bits of the column address are fed as a partial address and whose outputs are connected to the first control lines.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having memory cells disposed at crossover points of word lines and bit lines, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5687125 (1997-11-01), Kikuchi
patent: 5822268 (1998-10-01), Kirihata
patent: 5930194 (1999-07-01), Yamagata et al.
patent: 6134154 (2000-10-01), Iwaki et al.
patent: 6163496 (2000-12-01), Sasaki et al.
Dietrich Stefan
Schoniger Sabine
Schrogmeier Peter
Weis Christian
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Phung Anh
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