Static information storage and retrieval – Addressing – Sequential
Reexamination Certificate
1999-07-06
2001-02-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sequential
C365S230060
Reexamination Certificate
active
06188642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the field of integrated technology. Specifically, the invention relates to an integrated memory having a column decoder for decoding column addresses and for addressing corresponding bit lines.
Such an integrated memory in the form of a DR-AM is described and illustrated, for example, by Tietze and Schenk, “Electronic Circuits: Design and Applications,” FIG. 11.9, Springer-Verlag Berlin, 1991. As is generally customary, the RAM also has a row decoder for decoding row addresses and for addressing corresponding word lines. All the column addresses are supplied to the column decoder via a column address bus, while the row addresses are supplied to the row decoder via a row address bus.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the column addresses are supplied to the column decoder in another way.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of bit lines;
a column decoder connected to the bit lines for decoding column addresses and for addressing corresponding bit lines;
a first column address bus connected to the column decoder for transferring first column addresses to the column decoder;
a second column address bus connected to the column decoder for transferring second column addresses to the column decoder;
the column decoder addressing bit lines according to the first and second column addresses received through the first and second column buses respectively.
In other words, the integrated memory configuration according to the invention has a column decoder for decoding column addresses and for addressing corresponding bit lines. It also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder, the column decoder in each case addressing those bit lines which correspond to the first and second column addresses supplied to it.
In conventional memories, only one column address bus is provided for supplying all the column addresses. Hence, column addresses can be transferred to the column decoder only sequentially via this one column address bus. In the invention, however, the column addresses are transferred via two different column address buses.
The invention affords the advantage that temporally independent column addresses for addressing different bit lines can be transferred both via the first and via the second column address bus. Hence, for example, column addresses can be transferred to the column decoder via the first column address bus while the second column address bus is unavailable because it is required for other tasks. The invention makes it possible to reduce the time wasted on account of the signal delay times of the column addresses on the column address buses, because a column address can actually be transported to the column decoder via the first column address bus while the second column address bus is still providing a previous column address on the column decoder.
In accordance with an added feature of the invention, the first column addresses are supplied from the first column address bus to the column decoder in dependence on a first clock signal, and the second column addresses are supplied from the second column address bus to the column decoder in dependence on a second clock signal. In other words, the memory has a first clock signal, subject to which the first column addresses on the first column address bus are supplied to the column decoder, and a second clock signal, subject to which the second column addresses on the second column address bus are supplied to the column decoder. It is then possible to transport the first and second column addresses directly to the column decoder via the appropriate column address bus and then, using the first and second clock signals, to supply them at the desired instant of decoding by the column decoder. This has the advantage that long signal delay times caused by generally long address buses are no longer an issue for decoding by the column decoder if the first and the second clock signal are synchronized such that the corresponding column addresses have already been transferred to the column decoder via the address buses.
In accordance with an additional feature of the invention, there are provided:
address inputs for receiving the first column addresses connected to the first column address bus, and an address counter connected to the address inputs;
a control unit connected to the address inputs for loading one of the first column addresses applied to the address inputs into the address counter as a starting address thereof;
wherein the address counter is controlled by the second clock signal; and
wherein, for a specific number of cycles of the second clock signal, a respective content of the address counter is transferred to the second column address bus as one of the second column addresses.
The control unit thus loads one of the first column addresses applied to the address inputs into the address counter as its starting address and the address counter is controlled by the second clock signal. In addition, for a specific number of cycles of the second clock signal, the respective content of the address counter is transferred to the second column address bus as one of the second column addresses.
In this embodiment, the first column address can therefore be transferred directly from the address inputs to the column decoder via the first column address bus, and, at the same time as this is happening, this first column address can be loaded into the address counter as its starting address. This means that the column decoder is already addressing a bit line corresponding to the first column address while the first of the second column addresses is being generated by means of the address counter. With each cycle of the second clock signal, the content of the address counter is similarly supplied to the column decoder via the second column address bus, again subject to the second clock signal, whereupon the column decoder in each case addresses other bit lines corresponding to the second column addresses. This embodiment of the invention is thus suitable for implementing burst access to the bit lines of the memory, in which only one respective first column address is applied to the address inputs externally, and then a defined number of second column addresses are likewise transferred to the column decoder by means of the address counter and the second column address bus. Consequently, a number of the bit lines are always addressed in succession by the column decoder when one of the first column addresses is applied.
In accordance with another feature of the invention, the control unit for loading the starting address into the address counter is controlled by the first clock signal. In other words, the supply of the first column address to the column decoder as well as the loading of the first column address into the address counter are controlled by the first clock signal. This has the advantage that the decoding of the first column address and generation of the second column addresses take place simultaneously.
In accordance with a concomitant feature of the invention, the device includes a plurality of word lines and a row decoder for addressing the word lines; the first column address bus is also a row address bus usable, with time-division multiplexing to transfer the first column addresses, for additionally transferring row addresses from the address inputs to the row decoder for addressing the word lines; and the row addresses are supplied from the first column address bus to the row decoder in dependence on a third clock signal.
This development affords the advantage that, despite the presenc
Dietrich Stefan
Hein Thomas
Marx Thilo
Schoniger Sabine
Schrogmeier Peter
Greenberg Laurence A.
Lam David
Lerner Herbert L.
Nelms David
Siemens Aktiengesellschaft
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