Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-10-30
2001-09-18
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S222000, C365S190000
Reexamination Certificate
active
06292386
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated memory having cells of the 2-transistor/2-capacitor type.
U.S. Pat. No. 5,381,364 discloses an FRAM, i.e. FeRAM, type memory (ferroelectric random access memory) with cells of that type. In FRAMs, the memory capacitors comprise a ferro-electrical dielectric. An electrode of the two memory capacitors of each memory cell is connected to a respective bit line of a bit line pair via the controllable system of the appertaining selecting transistor. Control terminals of the two selecting transistors are connected to a common word line. The second electrodes of the two memory capacitors of each memory cell are connected to a common plate line. As a result, the potential at these electrodes of the memory capacitors is always the same during the operation of the memory.
SUMMARY OF THE INVENTION
In view of the forgoing it is an object of the invention to provide an integrated memory having cells of the 2-transistor/2-capacitor type which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and wherein the memory cells have a different structure from the prior art memory cells.
With the above and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
bit lines and word lines disposed to form points of intersection;
memory cells arranged at the points of intersection and each including a first transistor, a second transistor, a first capacitor, and a second capacitor;
the first transistor having a controlled path and the first capacitor having a first electrode connected to one of the bit lines via the controlled path of the first transistor;
the first capacitor having a second electrode connected to a first plate potential, wherein the first plate potential remains constant during an access of the memory cell;
the second transistor having a controlled path and the second capacitor having a first electrode connected to another of the bit lines via the controlled path of the second transistor;
the second capacitor having a second electrode connected to a second plate potential different from the first plate potential, wherein the second plate potential remains constant during an access of the memory cell;
the first and second transistors having control terminals connected to at least one of the word lines, whereby the first and second transistors are simultaneously switched to conduct upon an access to the memory cell; and
wherein a potential of the bit lines prior to the first and second transistors being switched to conduct is a bias potential between the first and second plate potentials and substantially at a mean value of the first and second plate potentials.
In other words, the electrodes of the novel memory cells which are averted from the transistors, of the two capacitors of each memory cell are connected to plate potentials that are different from one another during an accessing of the memory cell. These are a first plate potential and a second plate potential.
It is thus possible that a bias potential for the two bit lines that are connected to the memory cell can be selected between the first and the second potentials. In contrast, in conventional FRAMs, particularly those which function according to what is known as the VDD/2 concept, the selection of the bias potential of the bit lines is very limited. In those types of memories, the electrodes of the memory capacitors that are averted from the selecting transistors are permanently situated at half the value of the supply potential VPD. In order to obtain an meaningful evaluation of a difference signal that arises on the bit line pair in the read process, it is necessary to “precharge” both bit lines to ground prior to the read operation—that is to say, to discharge them. Therefore, in these conventional memories, the bias potential cannot be freely selected within a larger range of values. By contrast, in the invention the bias potential can be selected from a larger range; it need only be between the first and second plate potentials.
In the invention, the best results can be achieved for FRAMs that function according to the VDD/2 principle when the bias potential of the bit lines prior to a switching of the transistors of the memory cell to conduct corresponds to a mean value of the first and second plate potentials. A maximal difference signal then arises on the bit line pair during the read process.
In accordance with an added feature of the invention, in order to prevent data loss of the memory cells, a refresh mode of the memory is expediently provided, in which a reading and rewriting of the information that is stored in the memory cells occur.
In accordance with an additional feature of the invention, each memory cell comprises two shorting elements connected to short one of the capacitors while the first and second transistors of the respective memory cell are non-conductive.
This is an alternative to the refresh mode. Here, the memory cells each have two shorting elements, each of which serves to short one of the capacitors as long as the two transistors of the memory cell are not conductive. In ferroelectric memory capacitors, data loss is prevented as long as the potential at the two electrodes of the capacitors is the same; that is, as long as no voltage drops across the capacitor.
The control terminals of the two transistors of each memory cell can be connected either to a common word line or to different word lines that switch the transistors into conduct and block them simultaneously when the memory cell is accessed in that they are activated and deactivated at the same time, respectively.
In accordance with a concomitant feature of the invention, the memory is a ferroelectric memory, and the capacitors comprise a ferroelectric dielectric. In other words, the invention is suitable for ferroelectrical memories of the FRAM type, in particular those which function according to the VDD/2 principle. But it can also be applied to other memories, such as FRAMs that function according to what is known as the pulsed plate principle, in which the potential of the electrode of the memory capacitors that is averted from the selecting transistor is pulsed during a memory access; or to any other memories with memory cells of the 2-transistor/2-capacitor type.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having cells of the 2-transistor/2-capacitor type, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5381364 (1995-01-01), Chern et al.
patent: 5675530 (1997-10-01), Hirano et al.
patent: 41 10 407 A1 (1991-10-01), None
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
Tran Andrew Q.
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