Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-11-27
2007-11-27
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000, C714S719000
Reexamination Certificate
active
10920210
ABSTRACT:
An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of the memory banks. The test circuit includes a data generator for generating read comparison data. A plurality of comparison circuits are assigned to a different one of the memory banks to compare test data read from the assigned memory bank with the read comparison data. A first input of the respective comparison circuit can be connected to the secondary sense amplifier without interposition of the read/write data lines. A second input can be connected to the read/write data lines to receive the read comparison data supplied by the data generator. An output signal of the respective comparison circuit depends on the comparison result of a data comparison of the first and second inputs.
REFERENCES:
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patent: 6157584 (2000-12-01), Holst
patent: 6357027 (2002-03-01), Frankowsky
patent: 6721230 (2004-04-01), Weitz
patent: 2004/0015757 (2004-01-01), Ohlhoff et al.
patent: 10110272 (2002-09-01), None
Britt Cynthia
Edell Shapiro & Finnan LLC
Gandhi Dipakkumar
Infineon - Technologies AG
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