Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-09-22
2001-01-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06178124
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having a self-repair function.
To repair faulty memory cells, integrated memories have redundant word lines or redundant bit lines. These redundant lines can replace regular lines with faulty cells on an address basis. It is known practice to test integrated memories via their external connections using external testing devices and then to program the redundant elements externally using a laser beam. The redundancy circuit then has programmable elements in the form of laser fuses which are used to store the address of a line which is to be replaced. The laser fuses are electrical connection elements which can be severed at the end of the production process for the integrated memory using the laser beam. This methodv requires an external testing device for carrying out the memory cell test. It also has the disadvantage that the signals needed to carry out the test have to be transmitted via the external connections of the memory, which are restricted in number. This means that the bandwidth of the test signals is limited and such a test takes a relatively long time.
A memory having a self-repair function is disclosed in U.S. Pat. No. 5,313,424 to Adams et al. A self-test unit tests the memory cells in the memory and then stores the address of defective word lines in an appropriate address register. The memory is then supplied externally with an activation signal having a high potential level, and severable electrical connection elements (fuses), which are component parts of a redundancy circuit, are then destroyed to code the faulty word addresses stored in the address register. The fuses are destroyed with a high current that causes them to melt.
The self-test described in U.S. Pat. No. 5,313,424 for the memory with subsequent self-repair has the advantage that no external testing device is needed to carry out the memory cell test, and that the bandwidth for the test signals is not limited by the number of external connections of the memory. However, the results of the memory cell test, i.e. the addresses of the faulty word lines, remain “hidden” in the integrated memory. Accordingly, analysis of the faults which occur, which is of interest to the manufacturer of the memory, is not possible.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory which has a self-repair function, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows an external analysis of the faults discovered in the repair test.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory of an integrated circuit, comprising:
a plurality of memory cells combined to form individually addressable standard units;
a redundant unit for replacing one of the standard units on an address basis;
a self-test unit adapted to perform a function test on the memory cells and to analyze which of the standard units is to be replaced with the redundant unit;
a first memory unit for storing an address, determined by the self-test unit, of the standard unit to be replaced by the redundant unit;
an address bus; and
a comparison unit connected to the address bus and to outputs of the first memory unit, for comparing an address present on the address bus with the address stored in the first memory unit and for activating the redundant unit if the addresses match;
the first memory unit having at least one output connected to an output of the integrated circuit for outputting the address stored in the first memory unit.
In accordance with an added feature of the invention, there are provided a plurality of redundant units.
The integrated memory according to the invention is a component part of an integrated circuit and has memory cells which are combined to form individually addressable standard (normal) units. The redundant unit replaces one of the standard units on an address basis. The self-test unit performs a function test on the memory cells and an analysis as to which of the standard units is to be replaced by the redundant unit. The memory also has a first memory unit for storing the address, determined by the self-test unit, of the standard unit which is to be replaced by the redundant unit, and a comparison unit, which is connected to an address bus and to outputs of the first memory unit, for comparing an address present on the address bus with the address stored in the first memory unit and for activating the redundant unit if a match is recognized. In this arrangement, the first memory unit has at least one output which is connected to a corresponding output of the integrated circuit for outputting the respectively stored address.
The invention is suitable for any memories in which faulty units are repaired by, and readdressed to redundant units. The standard or redundant units can be word lines or bit lines or entire memory blocks of the memory, for example. The integrated memory may be a writable memory, for example, such as a DRAM, SRAM, flash memory or EEPROM.
The first memory unit of the integrated memory is used for a dual function:
Firstly, it stores the address of the faulty standard unit to be replaced and passes this to the comparison unit, so that the latter can activate the redundant unit if the appropriate address is present on the address bus. Secondly, the first memory unit is used to output the respectively stored address to outside the integrated circuit. Hence, if required, the manufacturer of the integrated circuit can ascertain whether faults were discovered during the self-test of the memory and whether a self-repair was carried out. It is also possible for the manufacturer to ascertain the address of the faults discovered.
In accordance with an additional feature of the invention, the first memory unit is a volatile memory unit, and a nonvolatile second memory unit for storing an address supplied from outside the integrated circuit, the second memory unit having at least one output which is connected to a corresponding input of the first memory unit for transmitting an address stored in the second memory unit to the first memory unit.
The fact that the first memory unit of the integrated memory is volatile means it stores the address, determined by the self-test unit, of the standard unit to be replaced in a nonpermanent manner. The memory according to the development also has a nonvolatile second memory unit for permanently storing an address which can be supplied from outside the integrated circuit, the second memory unit having at least one output which is connected to a corresponding input of the first memory unit, so that an address stored in the second memory unit can be transmitted to the first memory unit.
A volatile memory unit, such as an address register or address latch, can easily have information written to it by a self-test unit, since no voltages or large currents beyond the normal signal level of the memory are required for this. Provision of the second memory unit has the advantage that the self-test of the memory does not need to be repeated every time the first memory unit (for example after the supply voltage has been switched off) has lost the address stored in it. Since the first memory unit is volatile, it would otherwise be necessary, for example whenever the memory were initialized, to have the self-test determine once again the address of the standard units to be replaced. Since the first memory unit permits, via its output, the address stored in it to be output to outside the integrated circuit, this address can then be stored permanently in the second memory unit externally. To restore the memory content of the volatile first memory unit, for example whenever the memory is initialized after the supply voltage has been applied, all that is required then is for the address stored in the second memory unit to be transmitted to the first memory unit.
In accordance with another feature of the invent
Kaiser Robert
Schamberger Florian
Schneider Helmut
Greenberg Laurence A.
Lerner Herbert L.
Nelms David
Siemens Aktiengesllschaft
Stemer Werner H.
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