Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-05-18
2001-05-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S145000
Reexamination Certificate
active
06236607
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated memory having a reference potential, and to an operating method for such a memory.
U.S. Pat. Nos. 5,844,832 and 5,822,237 describe ferroelectric memories of the FRAM or FeRAM type (Ferroelectric Random Access Memory) of the 1-transistor/1-capacitor type. Such memories are constructed similarly to DRAMs (Dynamic Random Access Memories) but their storage capacitors have a ferroelectric dielectric. Their bit lines are connected in pairs to differential sense amplifiers. In the event of a read access, a datum is transferred from one of the memory cells to the sense amplifier via one of the bit lines of the bit line pairs, while a reference potential is generated on the other bit line of the bit line pair. The sense amplifier subsequently amplifies the differential signal present at its inputs to full logic levels.
In the circuits described in the two U.S. patents, the reference potential is generated by different states being stored in two reference memory cells connected to different bit lines. This means that the ferroelectric dielectric of the storage capacitors of the reference memory cells, which are constructed in exactly the same way as the normal memory cells of the memory, is polarized differently. Afterwards, the states stored in the reference memory cells are read out onto the associated bit lines and the two bit lines are short-circuited, with the result that a common reference potential is finally established on both bit lines.
According to U.S. Pat. No. 5,844,832, firstly the reference memory cells are read onto the associated bit lines by their selection transistors being turned on via a reference word line, and then the two bit lines are short-circuited in order to generate the reference potential. According to U.S. Pat. No. 5,822,237 the bit lines are short-circuited during a period of time in which the selection transistors of the reference memory cells are also in the on state. In another variant presented in U.S. Pat. No. 5,822,237, the short-circuiting transistor connects to one another not the two bit lines that are connected to the reference memory cells, but, within the reference memory cells, directly the storage capacitors thereof. In that variant, in order to generate the reference potential, firstly the short-circuiting transistor is turned on, so that charge balancing takes place between the two reference memory cells, before the reference word line is activated and the selection transistors of the reference memory cells are turned on. Before the selection transistors are turned on, the short-circuiting transistor is turned off.
In those prior art memories in which the short-circuiting of the bit lines or reference memory cells and the turning-on of their selection transistors are effected successively, a relatively long time period is required for generating the reference potential. In the other above-mentioned prior art memories, the selection transistors of the reference memory cells are in the on state the whole time while the short-circuiting transistor is in the on state and carries out complete charge balancing between the bit lines. This has the disadvantage that, during the charge balancing, the non-linear capacitances of the ferroelectric storage capacitors of the reference memory cells affect the reference potential to be generated. By contrast, the bit line capacitances are linear. In memories in which firstly the reference memory cells are read onto the bit lines and, after their selection transistors have been turned off, then the bit lines are short-circuited, a reference potential is established on the bit lines which corresponds to the arithmetic mean of the potentials established on the bit lines during the reading of the reference memory cells. As a result of the non-linear capacitances of the storage capacitors, by contrast, a different value of the reference potential is produced if the selection transistors and the short-circuiting transistor are simultaneously in the on state.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory of the above-described type and an associated operating method, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the reference potential is generated in a manner in which the influence of the non-linear capacitances of the storage capacitors of the reference memory cells is reduced by comparison with the prior art, and in which the reference potential can nevertheless be generated in a relatively short time.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
two bit lines and memory cells arranged along the two bit lines;
first and second reference memory cells each having a selection transistor connected to one of the bit lines;
a first switching element connecting the bit lines to one another;
a writing unit connected to the reference memory cells for storing a first state in the first reference memory cell and a second state in the second reference memory cell;
a control unit connected to the first switching element, the control unit generating a common reference potential on the two bit lines by first turning on the first switching element and the selection transistors of the two reference memory cells and, after a specific time period, turning off the selection transistors while the first switching element remains on and compensates for a potential difference between the two bit lines.
In other words, both the first switching element which short-circuits the two bit lines and the selection transistors of the two reference memory cells are firstly turned on. After a specific time period, the selection transistors are turned off, while the first switching element remains in the on state and compensates for a potential difference between the two bit lines.
The selection transistors of the reference memory cells are thus turned off at such an early point in time that complete charge balancing between the two bit lines has not yet taken place. Consequently, the influence of the non-linear storage capacitances of the reference memory cells on the reference potential that is established is less than if the selection transistors were in the on state until complete charge balancing between the two bit lines. Since both the selection transistors and the first switching element are simultaneously in the on state during the specific time period, the reading of the reference memory cells and the charge balancing between the bit lines are advantageously not effected sequentially but rather—at least partly—temporally in parallel. This results in a relatively short time being required to generate the reference potential.
It is favorable if the first switching element is turned on at the latest at the same time as the selection transistors. In that case, the charge balancing between the bit lines begins at the very point when the selection transistors are turned on.
In accordance with an added feature of the invention, the control unit which drives the first switching element and the selection transistors contains programmable elements for setting the specific time period. The programmable elements enable the specific time period to be chosen such that a desired reference potential is produced.
In accordance with an additional feature of the invention, the programmable elements are reversibly programmable elements. The specific time period can thus be changed, thereby enabling adaptation of the reference potential that is established.
In accordance with another feature of the invention, an evaluation circuit for determining the specific time period, the evaluation circuit ascertaining when a potential of the two bit lines has a same quantitative difference with respect to the desired reference potential with the selection transistors in an on state and the first switching element in an on state, and, depending on a determin
Esterl Robert
Manyoki Zoltan
Schlager Tobias
Greenberg Laurence A.
Infineion Technologies AG
Lam David
Lerner Herbert L.
Nelms David
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