Integrated memory having a circuit for testing the operation...

Details Integrated memory having a circuit for testing the operation... Integrated memory having a circuit for testing the operation...

2004-08-13

2008-11-18

Maskulinski, Michael C (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S723000

Reexamination Certificate

active

07454662

ABSTRACT:
An integrated memory includes a circuit for testing the operation of the memory, a register circuit is used for storing a bit combination, compression unit, to receive test data which have been read from the memory cells, and a memory unit to store a plurality of bits from a compressed bit fail map. Each of the bits is associated with a different address region. One of the bits registers an error data item within the associated address region. In addition, a decoder circuit is provided for receiving the compressed address and for accessing that bit in the memory unit, which is associated with a respective address region on the basis of the compressed address. A short evaluation time for a function test on the memory and flexible alignment with the individual memory size are made possible.

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patent: WO 98/03979 (1998-01-01), None

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