Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-05-30
2001-10-23
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S063000
Reexamination Certificate
active
06307771
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated memory having 2-transistor/2-capacitor memory cells.
U.S. Pat. No. 5,592,410 discloses an integrated memory of the FRAM (Ferroelectric Random Access Memory) type, which has memory cells of the 2-transistor/2-capacitor type. In that case, each memory cell is formed by two 1-transistor/1-capacitor memory cells disposed at crossover points of word lines and bit lines. In that memory, the 1-transistor/1-capacitor memory cells are disposed at each crossover point between the bit lines and the word lines. The two 1-transistor/1-capacitor memory cells of each 2-transistor/2-capacitor memory cell are connected to two bit lines of a bit line pair in each case. The two bit lines of each bit line pair are disposed adjacent one another.
The memory disclosed in U.S. Pat. No. 5,592,410 has the disadvantage that, given a prescribed dimensioning of the bit lines, of the word lines and also of the spacings between the bit lines and the word lines for the realization of the memory cells (that is to say for their selection transistors and storage capacitors), there is only a certain area available. That is because the structure of the memory cells has to be adapted to the structure prescribed by the word lines and bit lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory having 2-transistor/2-capacitor memory cells, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which, given a prescribed dimensioning of bit lines and word lines, there is more space available for a realization of the memory cells than in the case of the prior art described.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising word lines and bit lines intersecting each other at crossover points, the bit lines combined into bit line pairs, the bit line pairs interleaved by having at least one of the bit lines of one bit line pair disposed between the two bit lines of another bit line pair; 2-transistor/2-capacitor memory cells each having two 1-transistor/1-capacitor memory cells each disposed at a respective one of the crossover points; each of the two 1-transistor/1-capacitor memory cells of the 2-transistor/2-capacitor memory cells having a selection transistor connected to one of the two bit lines of a respective one of the bit line pairs and connected to at least one of the word lines; and a measure enabling the selection transistors to be simultaneously activated for simultaneously accessing the two 1-transistor/1-capacitor memory cells of one of the 2-transistor/2-capacitor memory cell.
This means that, in contrast to the prior art, the two bit lines of each bit line pair are not disposed adjacent one another, but rather are separated from one another by other bit lines. In other words, at least one bit line of another bit line pair is located between the two bit lines of each bit line pair.
The advantage of the invention is that a 1-transistor/1-capacitor memory cell does not have to be disposed at each crossover point between the word lines and bit lines in order to realize the 2-transistor/2-capacitor memory cells. therefore, given a prescribed dimensioning of the bit lines and word lines and the mutual spacing thereof, more space is available in the case of the memory according to the invention than if, as in the case of the prior art, the two 1-transistor/1-capacitor memory cells of each 2-transistor/2-capacitor memory cell were connected to bit lines disposed directly adjacent one another.
The two 1-transistor/1-capacitor memory cells of each 2-transistor/2-capacitor memory cell may, for example, be connected to two different word lines which are activated simultaneously in the event of an access. It is expedient, however, in accordance with another feature of the invention, if they are connected to a common word line, with the result that only the latter has to be activated in the event of the memory cell being accessed.
In accordance with a further feature of the invention, there are provided sense amplifiers which are each assigned to one of the bit line pairs and which have inputs that are connected to the associated bit lines in such a way that the corresponding connecting lines are crossed. The crossing of the connecting lines makes it possible for precisely one sense amplifier to be assigned to each bit line pair.
In accordance with a concomitant feature of the invention, each sense amplifier is assigned, in each case, to at least two of the bit line pairs and its inputs are connected to the associated bit lines of the two bit line pairs through a corresponding multiplexer in each case. The multiplexer makes it possible to avoid the transpositions or crossings of the connecting lines of the previously outlined embodiment of the invention. Moreover, the number of sense amplifiers required is smaller.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having 2-transistor/2-capacitor memory cells, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5592410 (1997-01-01), Verhaeghe et al.
patent: 5764561 (1998-06-01), Nishimura
patent: 690 31 847 (1998-05-01), None
Honigschmid Heinz
Schlager Tobias
Le Vu A.
Siemens Aktiengesellschaft
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