Integrated memory device with multi-sector selection commands

Details Integrated memory device with multi-sector selection commands Integrated memory device with multi-sector selection commands

2004-11-08

2008-11-25

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

07457908

ABSTRACT:
An integrated memory device is proposed. The memory device includes a flash memory having an address parallelism and a data parallelism; the flash memory is partitioned into a plurality of blocks each one including a plurality of sectors, which can be erased individually. A Low Pin Count communication interface is used to receive a command from an external bus, which has a transfer parallelism lower than the address parallelism and the data parallelism; the command includes a selection field for selecting each sector of one or more blocks individually. A control unit then executes an operation corresponding to the command in respect of each selected sector.

REFERENCES:
patent: 6172915 (2001-01-01), Tang et al.
patent: 2003/0093711 (2003-05-01), Harari et al.
“Intel Low Pin Count (LPC) Interface Specification” Aug. 2002, Revision 1.1, Document No. 251289-001.

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