Integrated memory control apparatus

Details Integrated memory control apparatus Integrated memory control apparatus

2007-11-19

2010-10-19

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S103000, C711S168000, C711S112000, C710S241000, C710S110000, C710S065000

Reexamination Certificate

active

07818529

ABSTRACT:
An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

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Computer memory. Encyclopædia Britannica. Encyclopædia Britannica Online. Encyclopædia Britannica, 2010. Web. Feb. 26, 2010 <http://www.search.eb.com/eb/article-252736>.

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