Integrated memory circuit with sequenced bitlines for stress tes

Details Integrated memory circuit with sequenced bitlines for stress tes Integrated memory circuit with sequenced bitlines for stress tes

1997-04-07

1998-04-28

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365 69, G11C 700

Patent

active

057454205

ABSTRACT:
An integrated circuit having a memory array comprised of a plurality of memory cells arranged in rows and columns and a logic circuitry including column decoder and read/write circuitry, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines extending from the memory array to the logic circuitry. In order to perform a complete voltage stress test of the memory array, inside the array true and complement bitlines are alternated so that every true bitline is adjacent exclusively to complement bitlines and every complement bitline is adjacent exclusively to true bitlines. According to a first embodiment of the invention, bitlines exiting from the memory array are connected directly to the logic circuitry, while according to a second embodiment, between the array and the logic circuitry, at least one pair of true and complement bitlines is twisted so that one bitline cross over the other. As a result, inside the memory array the true bitline of said at least one pair is adjacent exclusively to complement bitlines and the complement bitline of said at least one pair is adjacent exclusively to true bitlines.

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